TSL208R

512 y 1 LINEAR SENSOR ARRAY

TAOS031G − AUGUST 2011

7

The LUMENOLOGY

r Company

r

r

Copyright

E 2011, TAOS Inc.

www.taosinc.com

APPLICATION INFORMATION

Integration Time

The integration time of the linear array is the period during which light is sampled and charge accumulates on

each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature

of the TAOS TSL2xx linear array family. By changing the integration time, a desired output voltage can be

obtained on the output pin while avoiding saturation for a wide range of light levels.

Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity

to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the

functional block diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing

switch S1 (position 2).

At SI input (Start Integration), pixel 1 is accessed. During this event, S2 moves from position 1 (sampling) to

position 3 (holding). This holds the sampled voltage for pixel 1. Switch S1 for pixel 1 is then moved to position

2. This resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new

integration cycle. When the next clock period starts, the S1 switch is returned to position 1 to be ready to

start integrating again. S2 is returned to position 1 to start sampling the next light integration. Then the next pixel

starts the same procedure. The integration time is the time from a specific pixel read to the next time that pixel

is read again. If either the clock speed or the time between successive SI pulses is changed, the integration time

A new SI pulse can occur on the (n+1) clock causing a new cycle of integration/output to begin. Note that the

time between successive SI pulses must not exceed the maximum integration time of 100 msec.

The minimum integration time for any given array is determined by time required to clock out all the pixels in

the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore,

the minimum integration period is simply a function of the clock frequency and the number of pixels in the array.

A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation

on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency

of 5 MHz.

The minimum integration time can be calculated from the equation:

1

maximum clock frequency

n

where:

n

is

the number of pixels

In the case of the TSL208R, the minimum integration time would be:

512 + 102.4ms

It is important to note that not all pixels will have the same integration time if the clock frequency is varied while

data is being output.