Data Sheet S11822EJ4V0DS00

8

PIN NAMES

ACK_B

: Read/write Cycle Receive Acknowledge

AIN1

: External Filter Connection

CS

: Chip Select

DS_B

: Data Strobe

EMPTY_B

: Output Buffer Empty

FULL_B

: Buffer Full

GND

: Ground

GND-RPE

: Ground for Receive PECL Buffer

GND-CR

: Ground for Clock Recovery Circuit

GND-CS

: Ground for Clock Synthesis

GND-SP

: Ground for Serial/Parallel Circuit

GND-TPE

: Ground for Transmit PECL Buffer

JCK

: JTAG Clock

JDI

: JTAG Data Input

JDO

: JTAG Data Output

JMS

: JTAG Mode Select

JRST_B

: JTAG Reset

MADD0-MADD6 : Management Interface Address Bus

MD0-MD7

: Management Interface Data Bus

MSEL

: Management Interface Mode Select

PHINT_B

: Physical Interrupt

PHYALM0-

: PHY Alarm Detection

PHYALM2

PMDALM

: PMD Device Alarm

PSEL0, PSEL1 : PMD Mode Select

RADD0-RADD4 : Receive PHY Device Address

RCIC

: Receive Clock Input Complement

RCIT

: Receive Clock Input True

RCL

: Internal Receive System Clock

RCLAV

: Receive Cell Available

RCLK

: Receive Data Transferring Clock

RD_B

: Read Select

RDIC

: Receive Data Input Complement

RDIT

: Receive Data Input True

RDO0-RDO7

: Receive Data Output

RDY_B

: Ready Signal

REFCLK

: System Clock

RENBL_B

: Receive Data Enable

RESET_B

: System Reset

RPC

: Receive Parallel Data Clock

RPD0-RPD7

: Receive Parallel Data

RSOC

: Receive Start Address of ATM Cell

RxFP

: Receive Frame Pulse

R/W_B

: Read/write Control

TADD0-TADD4 : Transmit PHY Device Address

TCL

: Internal Transmit System Clock

TCLAV

: Transmit Cell Available

TCLK

: Transmit Data Transferring Clock

TCOC

: Transmit Clock Output Complement

TCOT

: Transmit Clock Output True

TDI0-TDI7

: Transmit Data Input from the ATM Layer

TDOC

: Transmit Data Output Complement

TDOT

: Transmit Data Output True

TENBL_B

: Transmit Data Enable

TEST0-TEST2

: Test Mode Pin

TFC

: Transmit Reference Clock

TFKC

: Transmit Reference Clock Complement

TFKT

: Transmit Reference Clock True

TFSS

: Transmit Frame Set Signal

TPC

: Transmit Parallel Data Clock

TPD0-TPD7

: Transmit Parallel Data

TSOC

: Transmit Start Address of ATM Cell

TxFP

: Transmit Frame Pulse

UMPSEL

: Utopia Multi-PHY Mode Select

VDD

: Supply Voltage for Logic Circuit

VDD-RPE

: Voltage Supply for Receive PECL Buffer

VDD-CR

: Voltage Supply for Clock Recovery Circuit

VDD-CS

: Voltage Supply for Clock Synthesis

VDD-SP

: Voltage Supply for Serial/Parallel Circuit

VDD-TPE

: Voltage Supply for Transmit PECL Buffer

WR_B

: Write Select