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PIC16C925-S/CL 数据表(PDF) 156 Page - Microchip Technology

部件名 PIC16C925-S/CL
功能描述  64/68-Pin CMOS Microcontrollers with LCD Driver
PDF  182 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

PIC16C925-S/CL 数据表(HTML) 156 Page - Microchip Technology

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PIC16C925/926
DS39544A-page 154
Preliminary
 2001 Microchip Technology Inc.
TABLE 15-8:
SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
70
TssL2scH,
TssL2scL
SS
↓ to SCK↓ or SCK↑ input
TCY
——
ns
71
71A
TscH
SCK input high time (Slave
mode)
Continuous
1.25TCY + 30
——
ns
Single Byte
40
——
ns
72
72A
TscL
SCK input low time (Slave
mode)
Continuous
1.25TCY + 30
——
ns
Single Byte
40
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
50
——
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
50
——
ns
75
TdoR
SDO data output rise time
—
10
25
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS
↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (Master mode)
—
10
25
ns
79
TscF
SCK output fall time (Master mode)
—
10
25
ns
80
TscH2doV,
TscL2doV
SDO data output valid after SCK edge
——
50
ns
81
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
——
ns
82
TssL2doV
SDO data output valid after SS
↓ edge
——
50
ns
83
TscH2ssH,
TscL2ssH
SS
↑ after SCK edge
1.5TCY + 40
——
ns
84
Tb2b
Delay between consecutive bytes
1.5TCY + 40
——
ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.



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