EM342-RTR datasheet(104/143 Pages) SILABS

104 / 143 page

EM342

104

Rev 1.0

Table 9.2 provides a map of all peripheral interrupts. This map lists the top-level NVIC Interrupt bits and, if there is

one, the corresponding second-level EM Interrupt register bits that feed the top-level interrupts.

9.3. Non-Maskable Interrupt (NMI)

The non-maskable interrupt (NMI) is a special case. Despite being one of the 10 standard ARM® CortexTM-M3

NVIC interrupts, it is sourced from the Event Manager like a peripheral interrupt. The NMI has two second-level

sources; failure of the 24 MHz crystal and watchdog low water mark.

1. Failure of the 24 MHz crystal: If the EM342's main clock, SYSCLK, is operating from the 24 MHz crystal

and the crystal fails, the EM342 detects the failure and automatically switches to the internal 12 MHz RC

clock. When this failure detection and switch has occurred, the EM342 triggers the CLK24M_FAIL second-

Table 9.2. NVIC and EM Peripheral Interrupt Map

NVIC Interrupt

(Top-Level)

EM Interrupt

(Second-Level)

NVIC Interrupt

(Top-Level)

EM Interrupt

(Second-Level)

INT_DEBUG

INT_SLEEPTMR

INT_IRQD

INT_BB

INT_IRQC

INT_MGMT

Reserved

Reserved.

INT_IRQA

Reserved

INT_MACRX

INT_MACTX

INT_MACTMR

INT_SEC

Reserved

INT_SC1

INT_SC1FLAG register

INT_SC1PARERR

INT_SC1FRMERR

INT_SCTXULDB

INT_SCTXULDA

INT_SCRXULDB

INT_SCRXULDA

INT_SCNAK

INT_SCCDMFIN

INT_SCTXFIN

INT_SCRXFIN

INT_SCTXUND

INT_SCRXOVF

INT_SCTXIDLE

INT_SCTXFREE

INT_SCRXVAL

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