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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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RPC564L60L5BOSY 数据表(PDF) 125 Page - STMicroelectronics |
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RPC564L60L5BOSY 数据表(HTML) 125 Page - STMicroelectronics |
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125 / 137 page  DocID026934 Rev 1 125/137 RPC56EL60L5 Electrical characteristics 136 Figure 29. External interrupt timing 3.20.6 DSPI timing IRQ 1 2 3 Table 38. DSPI timing No. Symbol Parameter Conditions Min Max Unit 1tSCK D DSPI cycle time Master (MTFE = 0) 62 — ns D Slave (MTFE = 0) 62 — D Slave Receive Only Mode(1) 16 — 2tCSC D PCS to SCK delay — 16 — ns 3tASC D After SCK delay — 16 — ns 4tSDC D SCK duty cycle — tSCK/2 - 10 tSCK/2 + 10 ns 5tA D Slave access time SS active to SOUT valid — 40 ns 6tDIS D Slave SOUT disable time SS inactive to SOUT High-Z or invalid — 10 ns 7 tPCS C D PCSx to PCSS time — 13 — ns 8 tPAS C DPCSS to PCSx time — 13 — ns 9tSUI D Data setup time for inputs Master (MTFE = 0) 20 — ns Slave 2— Master (MTFE = 1, CPHA = 0) 5— Master (MTFE = 1, CPHA = 1) 20 — 10 tHI D Data hold time for inputs Master (MTFE = 0) –5 — ns Slave 4 — Master (MTFE = 1, CPHA = 0) 11 — Master (MTFE = 1, CPHA = 1) –5 — |
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