ST7MC2 datasheet(266/308 Pages) STMICROELECTRONICS

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ST7MC1/ST7MC2

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12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network protects the device against parasitic resets.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

0.3xVDD

VIH

Input high level voltage

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

VOL

Output low level voltage 3)

VDD=5V

IIO=+5mA

0.5

1.2

IIO=+2mA

0.2

0.5

IIO

Driving current on RESET pin

RON

Weak pull-up equivalent resistor

VIN=VSS, VDD=5V

150

Ω

tw(RSTL)out Generated reset pulse duration

Internal reset sources

µs

th(RSTL)in External reset pulse hold time

2.5

µs

tg(RSTL)in Filtered glitch duration

450

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