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STM32F427AI 数据表(PDF) 175 Page - STMicroelectronics |
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STM32F427AI 数据表(HTML) 175 Page - STMicroelectronics |
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175 / 239 page  DocID024030 Rev 9 175/238 STM32F427xx STM32F429xx Electrical characteristics 197 Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 94 through Table 97 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • BurstAccessMode = FMC_BurstAccessMode_Enable; • MemoryType = FMC_MemoryType_CRAM; • WriteBurst = FMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F4xx reference manual : RM0090) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 90 MHz). Table 93. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2) 1. CL = 30 pF. 2. Guaranteed by characterization results. Symbol Parameter Min Max Unit tw(NE) FMC_NE low time 9THCLK 9THCLK+0.5 ns tw(NWE) FMC_NWE low time 7THCLK 7THCLK+2 ns tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK+1.5 - ns th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK–1 - ns |
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