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STM32L072VB 数据表(PDF) 102 Page - STMicroelectronics |
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STM32L072VB 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 147 page  Electrical characteristics STM32L072xx 102/147 DocID027100 Rev 3 Figure 31. Typical connection diagram using the ADC 1. Refer to Table 64: ADC characteristics for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 32 or Figure 33, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA) |
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