STM32L072CB datasheet(112/147 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L072xx

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DocID027100 Rev 3

Figure 35. SPI timing diagram - slave mode and CPHA = 0

Table 77. SPI characteristics in voltage Range 3 (1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

2(2)

Duty(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4*Tpclk

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2*Tpclk

tw(SCKH)

tw(SCKL)

SCK high and low time

Master mode

Tpclk-2

Tpclk

Tpclk+2

tsu(MI)

Data input setup time

Master mode

1.5

tsu(SI)

Slave mode

th(MI)

Data input hold time

Master mode

13.5

th(SI)

Slave mode

ta(SO

Data output access time

Slave mode

tdis(SO)

Data output disable time

Slave mode

tv(SO)

Data output valid time

Slave mode

tv(MO)

Master mode

th(SO)

Data output hold time

Slave mode

th(MO)

Master mode

1. Guaranteed by characterization results.

2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit

into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates

with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

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