SPC560P54X datasheet(104/105 Pages) STMICROELECTRONICS

104 / 105 page

Revision history

SPC56xP54x, SPC56xP60x

104/105

DocID18340 Rev 6

21-Nov-2012

In the cover page, replaced “64 MHz, dual issue, 32-bit CPU core

complex” with “64 MHz, single issue, 32-bit CPU core complex”

Table 9: Absolute maximum ratings, updated TVDD entry

Table 22: DC electrical characteristics (3.3 V, NVUSRO[PAD3V5V]=1):



Updated conditions value of VOL_F to 11 mA

Updated conditions value of VOH_F to – 11 mA

Table 24: Peripherals supply current (5 V and 3.3 V):



Replaced all occurrences of IDD_BV in this table with IDD_HV

Replaced all occurrences of VDD_BV in this table with

VDD_HV_REG.

Figure 40: Ordering information scheme, fixed typo in the footnote.

18-Sep-2013

Updated Disclaimer.

15-Jun-2016

Added “AEC-Q10x qualified” in Features section.

In Table 2: SPC56xP54x/SPC56xP60x device comparison added

footnote “LinFlex_1 is Master Only.” related to row “LINFlex modules”

Updated Table 3: SPC56xP54x/SPC56xP60x device configuration

difference

Figure 2: LQFP176 pinout (top view):

– Changed PB[4] to TDO

– Changed PB[5] to TDI

– Changed pins 71,72 to NC

– Changed pins 87,88 to NC

In Section 1.5.27: Nexus development interface (NDI), added note “At

least one TCK clock is necessary for the EVTI signal to be

recognized by the MCU.” for EVTI pin.

In Table 7: Pin muxing:

– Replaced “PCR register” with “PCR No.”

– Updated “CS3” with “CS3_4” function related to A[2] port pin

– In column “I/O direction”, added “O” for “DSPI_1” peripheral

– In “Functions” column related to D[12] port pin, changed DS7_1 to

CS7_1

Table 44. Document revision history (continued)

Date

Revision

Substantive changes

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