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OMAP3530ECBBALPD 数据表(PDF) 104 Page - Texas Instruments

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部件名 OMAP3530ECBBALPD
功能描述  Applications Processors
PDF  265 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBBALPD 数据表(HTML) 104 Page - Texas Instruments

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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1
BALL BOTTOM
BALL BOTTOM
BALL BOTTOM
)
(CBB Pkg.)
(CBC Pkg.)
(CUS Pkg.)
mm3_rxdp
Vplus receive data (not used in 3- or 4-pin configurations)
IO
AH3
M3
NA(2)
mm3_rxrcv
Differential receiver signal input (not used in 3-pin mode)
IO
AD1
U4
NA
mm3_txse0
Single-ended zero. Used as VM in 4-pin VP_VM mode.
IO
AE1
V3
NA
mm3_txdat
USB data. Used as VP in 4-pin VP_VM mode.
IO
AD2
R3
NA
mm3_txen_n
Transmit enable
IO
AC1
T3
NA
MM_FSUSB2
mm2_rxdm
Vminus receive data (not used in 3- or 4-pin configurations)
IO
AH7
AF7
AD11
mm2_rxdp
Vplus receive data (not used in 3- or 4-pin configurations)
IO
AF7
AF6
AC9
mm2_rxrcv
Differential receiver signal input (not used in 3-pin mode)
IO
AG8
AF9
AC11
mm2_txse0
Single-ended zero. Used as VM in 4-pin VP_VM mode.
IO
AH8
AE9
AD12
mm2_txdat
USB data. Used as VP in 4-pin VP_VM mode.
IO
AB2
T8
R5
mm2_txen_n
Transmit enable
IO
V3
V9
M4
MM_FSUSB1
mm1_rxdm
Vminus receive data (not used in 3- or 4-pin configurations)
IO
AG9
V2
AD5
mm1_rxdp
Vplus receive data (not used in 3- or 4-pin configurations)
IO
AF10
AB2
AC1
mm1_rxrcv
Differential receiver signal input (not used in 3-pin mode)
IO
AF11
AC3
AD6
mm1_txse0
Single-ended zero. Used as VM in 4-pin VP_VM mode.
IO
AG12
AD4
AC6
mm1_txdat
USB data. Used as VP in 4-pin VP_VM mode.
IO
AH12
AD3
AC7
mm1_txen_n
Transmit enable
IO
AH14
AD2
AD9
HSUSB3_TLL
hsusb3_tll_clk
Dedicated for external transceiver 60-MHz clock input to PHY
O
W8
W2
NA
hsusb3_tll_stp
Dedicated for external transceiver Stop signal
I
AH3
M3
NA
hsusb3_tll_dir
dedicated for external transceiver Data direction control from
O
AF3
L3
NA
PHY
hsusb3_tll_nxt
Dedicated for external transceiver Next signal from PHY
O
AE3
K3
NA
hsusb3_tll_data0
Dedicated for external transceiver Bidirectional data bus
IO
AD1
U4
NA
hsusb3_tll_data1
Dedicated for external transceiver Bidirectional data bus
IO
AE1
V3
NA
hsusb3_tll_data2
Dedicated for external transceiver Bidirectional data bus
IO
AD2
R3
NA
hsusb3_tll_data3
Dedicated for external transceiver Bidirectional data bus
IO
AC1
T3
NA
hsusb3_tll_data4
Dedicated for external transceiver Bidirectional data bus
IO
AF6
P3
NA
hsusb3_tll_data5
Dedicated for external transceiver Bidirectional data bus
IO
AE6
N3
NA
hsusb3_tll_data6
Dedicated for external transceiver Bidirectional data bus
IO
AF5
V3
NA
hsusb3_tll_data7
Dedicated for external transceiver Bidirectional data bus
IO
AE5
W3
NA
HSUSB2
hsusb2_clk
Dedicated for external transceiver 60-MHz clock input to PHY
O
AE7
AE4
AC3
hsusb2_stp
Dedicated for external transceiver Stop signal
O
AF7
AF6
AC9
hsusb2_dir
Dedicated for external transceiver Data direction control from
I
AG7
AE6
AC10
PHY
hsusb2_nxt
Dedicated for external transceiver Next signal from PHY
I
AH7
AF7
AD11
hsusb2_data0
Dedicated for external transceiver Bidirectional data bus
IO
AG8
AF9
AC11
hsusb2_data1
Dedicated for external transceiver Bidirectional data bus
IO
AH8
AE9
AD12
hsusb2_data2
Dedicated for external transceiver Bidirectional data bus
IO
AB2
T8
R5
hsusb2_data3
Dedicated for external transceiver Bidirectional data bus
IO
V3
V9
M4
hsusb2_data4
Dedicated for external transceiver Bidirectional data bus
IO
Y2
W8
N4
additional signals for 12-pin ULPI operation
hsusb2_data5
Dedicated for external transceiver Bidirectional data bus
IO
Y3
U8
N3
additional signals for 12-pin ULPI operation
hsusb2_data6
Dedicated for external transceiver Bidirectional data bus
IO
Y4
V8
M5
additional signals for 12-pin ULPI operation
hsusb2_data7
Dedicated for external transceiver Bidirectional data bus
IO
AA3
W7
N5
additional signals for 12-pin ULPI operation
HSUSB2_TLL
hsusb2_tll_clk
Dedicated for external transceiver 60-MHz clock input to PHY
O
AE7
AE4
AC3
104
TERMINAL DESCRIPTION
Copyright © 2008–2013, Texas Instruments Incorporated
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Product Folder Links: OMAP3530 OMAP3525



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