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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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R5F100JF 数据表(PDF) 155 Page - Renesas Technology Corp |
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R5F100JF 数据表(HTML) 155 Page - Renesas Technology Corp |
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155 / 202 page  RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105 C) Page 155 of 196 R01DS0131EJ0330 Rev.3.30 Mar 31, 2016 UART mode bit width (during communication at different potential) (reference) TxDq RxDq Baud rate error tolerance Baud rate error tolerance Low-bit width High-/Low-bit width High-bit width 1/Transfer rate 1/Transfer rate Remarks 1. Rb[ ]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. |
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