## Understanding EMIO (Extended Multiplexed I/O) In the context of Adaptive SoCs (System on Chips) and FPGAs—most notably the **Xilinx Zynq-7000** and **Zynq UltraScale+ MPSoC** architectures—**EMIO** is a critical interface bridge. It allows the Processing System (PS/the ARM cores) to access the Programmable Logic (PL/the FPGA fabric) through the I/O peripherals. --- ### 1. The Core Concept Modern SoCs are divided into two main domains: 1. **PS (Processing System):** The fixed-logic CPU and its hard-coded peripherals (UART, I2C, SPI, GPIO). 2. **PL (Programmable Logic):** The flexible FPGA fabric where you build custom hardware. **MIO (Multiplexed I/O)** connects the PS peripherals directly to dedicated external pins on the chip. However, these pins are limited. **EMIO (Extended MIO)** allows those same PS peripherals to be routed into the FPGA fabric instead of dedicated pins. ### 2. Why Use EMIO? | Feature | MIO (Dedicated) | EMIO (Extended) | | :--- | :--- | :--- | | **Pin Access** | Fixed, dedicated hardware pins. | Flexible, uses FPGA fabric pins. | | **Availability** | Limited number (usually 54 pins). | Extensive (up to 64-95+ pins depending on chip). | | **Customization** | No logic can be added between PS and pin. | Custom logic/IP can be inserted in the path. | | **Speed** | High speed, low latency. | Slightly higher latency due to FPGA routing. | --- ### 3. Functional Breakdown When you enable EMIO for a specific peripheral (e.g., a GPIO bank or a UART controller), the internal signals are "exported" to the PL. This provides several electronic design advantages: * **Pin Expansion:** If you run out of physical MIO pins for your SD card or SPI sensor, you can route the signals through EMIO to any available FPGA I/O pin. * **Signal Transformation:** You can intercept the EMIO signals within the PL to perform logic operations, such as level shifting, signal inverting, or multiplexing before the signal reaches a physical pin. * **Internal Communication:** You can use EMIO to allow the CPU to "talk" directly to a custom IP block you built in the FPGA, treating that block like a simple GPIO device. --- ### 4. Implementation Example (GPIO) In a typical Zynq design, GPIO is divided into banks: * **Bank 0 & 1:** Usually mapped to **MIO** (connected to fixed pins). * **Bank 2 & 3:** Usually mapped to **EMIO** (connected to the FPGA fabric). ```c // Example Pseudo-code to write to an EMIO pin from the ARM CPU #define EMIO_GPIO_PIN 54 // EMIO starts after the 54 MIO pins XGpioPs_WritePin(&GpioInstance, EMIO_GPIO_PIN, 0x1); // This sends a 'high' signal into the FPGA fabric via the EMIO interface ``` --- ### 5. Hardware Constraints While EMIO is versatile, designers must keep in mind: * **Timing:** Signals passing through the PL are subject to FPGA routing delays and must meet timing constraints set in tools like Vivado. * **I/O Standards:** Because EMIO signals end up on FPGA pins, you must manually define the voltage standards (e.g., LVCMOS 3.3V vs 1.8V) in the Constraints file (.XDC).