The **EP-R2** (EdgePoint R2) is part of Ubiquiti’s EdgeMAX series, specifically designed as a WISP (Wireless Internet Service Provider) router for outdoor tower installations. It integrates routing, switching, and PoE distribution into a single weather-resistant chassis. --- ### 1. Core Hardware Components The electronic architecture of the EP-R2 is built to handle high-throughput traffic and power delivery in harsh environments. | Component | Description | | :--- | :--- | | **Processor (CPU)** | Dual-Core 880 MHz, MIPS1004Kc. | | **System Memory** | 256 MB DDR3 RAM. | | **Code Storage** | 256 MB NAND Flash. | | **Switch Chip** | Integrated hardware offloading for Layer-2 switching performance. | --- ### 2. Interface and Connectivity The EP-R2 features a mix of copper and fiber ports to accommodate different backhaul and local link scenarios. * **Ethernet Ports:** 2x 10/100/1000 RJ45 ports. * **SFP Ports:** 1x 1Gbps SFP port for fiber connectivity (ideal for long-distance tower runs to avoid EMI). * **Console Port:** 1x RJ45 Serial port for out-of-band management. --- ### 3. Power Management (PoE) One of the most critical electronic aspects of the EP-R2 is its power distribution capability. It serves as a power hub for radios mounted on the same tower. | Feature | Specification | | :--- | :--- | | **Power Input** | (1) DC Terminal Block or (1) RJ45 (eth0) via PoE. | | **Input Voltage** | 24VDC, 3A (Terminal Block) or 24V Passive PoE. | | **PoE Output** | Passive 24V / 2-Pair or 4-Pair. | | **Max PoE Wattage** | Up to 24W per port (Eth1). | --- ### 4. Electronic Protection Systems Because the EP-R2 is mounted outdoors on metal towers (which act as lightning rods), its internal circuitry includes specific protection mechanisms: * **ESD/EMP Protection:** Air: ± 24 kV, Contact: ± 24 kV. * **Operating Temperature:** Internal components are rated for -40 to 65° C (-40 to 149° F). * **Grounding:** Dedicated grounding point to shunt surge voltage away from the main logic board. --- ### 5. Functional Block Diagram (Logical) The electronics are organized to separate the **Control Plane** (CPU/RAM) from the **Data Plane** (Switching silicon). ```mermaid graph TD A[DC Power Input / PoE In] --> B[Power Regulation Module] B --> C[CPU: Dual-Core 880MHz] B --> D[PoE Out Control] C --> E[256MB DDR3 RAM] C --> F[Gigabit Ethernet Ports x2] C --> G[SFP Fiber Port x1] F --> D ```