The **SAP-1 (Simple-As-Possible 1)** computer is a classic educational architecture designed to teach the fundamentals of how a CPU operates. The "R2" usually refers to a specific revision or iteration (Revision 2) often found in digital electronics kits or Ben Eater-style breadboard builds. Below is an explanation of the core electronic parts and functional blocks of the SAP-1 architecture. --- ## 1. Core Component Breakdown The SAP-1 is a 8-bit computer that utilizes standard **74LS series (TTL)** integrated circuits. | Module | Primary Function | Common ICs Used | | :--- | :--- | :--- | | **Clock** | Generates the timing pulses for the system. | NE555 Timer, 74LS04 (Inverters) | | **Program Counter** | Keeps track of the memory address of the next instruction. | 74LS161 (4-bit binary counter) | | **MAR (Memory Address Reg)** | Stores the address of the data being accessed. | 74LS157 (Mux), 74LS173 (Registers) | | **RAM** | Stores 16 bytes of data/instructions. | 74189 or 6116 (SRAM) | | **Instruction Register** | Holds the current instruction opcode. | 74LS173 (4-bit D-type Register) | | **Accumulator (A)** | Primary register for arithmetic operations. | 74LS173, 74LS245 (Bus Transceiver) | | **ALU** | Performs addition and subtraction. | 74LS283 (4-bit Adders), 74LS86 (XOR) | | **Output Register** | Displays the final result to the user. | 74LS173, 74LS47 (BCD to 7nd Seg) | --- ## 2. Detailed Module Descriptions ### A. The Control Unit (The Brain) The control unit is responsible for the **Fetch-Execute cycle**. In a physical build, this is often implemented using a **Control Matrix** (Diode logic or EEPROMs). - **Function:** It decodes the 4-bit instruction and activates the specific "Enable" (E) and "Load" (L) pins on other chips to move data across the bus. ### B. The W-Bus (Common Bus) The "W-Bus" is the backbone of the SAP-1. It is an 8-bit bidirectional path. - **Electronic Part:** Usually implemented using **74LS245** Octal Bus Transceivers. These allow data to flow onto the bus only when the "Output Enable" pin is pulled low, preventing signal contention. ### C. Arithmetic Logic Unit (ALU) The ALU in the SAP-1 is strictly for Addition and Subtraction. - **Logic:** It uses 4-bit binary adders (**74LS283**) cascaded for 8-bit math. - **Subtraction:** Achieved using 2's complement logic via XOR gates (**74LS86**) to invert the bits of the B-register. --- ## 3. Programming & Data Flow The SAP-1 utilizes a 16x8 memory structure. This means it has 16 memory addresses, each capable of holding 8 bits of data. ```text [ Address ] [ Instruction / Data ] 0000 (0) : LDA 1111 (Load RAM address 15 into A) 0001 (1) : ADD 1110 (Add RAM address 14 to A) 0010 (2) : OUT (Output the result) 0011 (3) : HLT (Halt the clock) ``` --- ## 4. Power and Signal Integrity In the **R2** versions, focus is often placed on: - **Bypass Capacitors:** Placing 0.1μF capacitors across VCC and GND for every IC to reduce switching noise. - **Pull-up Resistors:** Ensuring that floating inputs (especially on the 74LS series) are tied to 5V to prevent erratic behavior.