GENERAL DESCRIPTION
The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.

FEATURES
   Output frequency: <1 MHz to 1 GHz
   Start-up frequency accuracy: <±100 ppm (determined by
      VCXO reference accuracy)
   Zero delay operation
      Input-to-output edge timing: <150 ps
   14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS
   14 dedicated output dividers with jitter-free adjustable delay
   Adjustable delay: 63 resolution steps of ½ period of VCO
      output divider
   Output-to-output skew: <50 ps
   Duty cycle correction for odd divider settings
   Automatic synchronization of all outputs on power-up
   Absolute output jitter: <200 fs at 122.88 MHz
      Integration range: 12 kHz to 20 MHz
   Distribution phase noise floor: −160 dBc/Hz
   Digital lock detect
   Nonvolatile EEPROM stores configuration settings
   SPI- and I²C-compatible serial control port
   Dual PLL architecture
      PLL1
         Low bandwidth for reference input clock cleanup with
            external VCXO
         Phase detector rate up to130 MHz
         Redundant reference inputs
         Automatic and manual reference switchover modes
            Revertive and nonrevertive switching
         Loss of reference detection with holdover mode
         Low noise LVCMOS output from VCXO used for RF/IF
            synthesizers
      PLL2
         Phase detector rate up to 259 MHz
         Integrated low noise VCO

APPLICATIONS
   LTE and multicarrier GSM base stations
   Wireless and broadband infrastructure
   Medical instrumentation
   Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
   Low jitter, low phase noise clock distribution
   Clock generation and translation for SONET, 10Ge, 10G FC,
      and other 10 Gbps protocols
   Forward error correction (G.710)
   High performance wireless transceivers
   ATE and high performance instrumentation