Description
The ispLSI 2128V is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions.

Features
• HIGH DENSITY PROGRAMMABLE LOGIC
   — 6000 PLD Gates
   — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs
   — 128 Registers
   — High Speed Global Interconnect
   — Wide Input Gating for Fast Counters, State
      Machines, Address Decoders, etc.
   — Small Logic Block Size for Random Logic
• 3.3V LOW VOLTAGE 2128 ARCHITECTURE
   — Interfaces with Standard 5V TTL Devices
   — The 128 I/O Pin Version is Fuse Map Compatible
      with 5V ispLSI 2128
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   — fmax = 80 MHz Maximum Operating Frequency
   — tpd = 10 ns Propagation Delay
   — Electrically Erasable and Reprogrammable
   — Non-Volatile
   — 100% Tested at Time of Manufacture
   — Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
   — 3.3V In-System Programmability (ISP™) Using
      Boundary Scan Test Access Port (TAP)
   — Open-Drain Output Option for Flexible Bus Interface
      Capability, Allowing Easy Implementation of
      Wired-OR or Bus Arbitration Logic
   — Increased Manufacturing Yields, Reduced Time-to
      Market and Improved Product Quality
   — Reprogram Soldered Devices for Faster Prototyping
• THE EASE OF USE AND FAST SYSTEM SPEED OF
   PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS
   — Enhanced Pin Locking Capability
   — Three Dedicated Clock Input Pins
   — Synchronous and Asynchronous Clocks
   — Programmable Output Slew Rate Control
   — Flexible Pin Placement
   — Optimized Global Routing Pool Provides Global
      Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM
   PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
   SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
   — Superior Quality of Results
   — Tightly Integrated with Leading CAE Vendor Tools
   — Productivity Enhancing Timing Analyzer, Explore
      Tools, Timing Simulator and ispANALYZER™
   — PC and UNIX Platforms