GENERAL DESCRIPTION
The ML7204-001 is a speech CODEC for VoIP. As a speech CODEC, this LSI allows selection of G.729.A/G711 and supports the PLC (Packet Loss Concealment) function.
With an echo canceler that handles 32 ms-delay and FSK detection/generation, DTMF detection/generation, and tone detection/generation functions, the ML7204-001 is the most suitable LSI for adding the VoIP function to TAs and routers.

FEATURES
• Power supply voltage
   Digital power supply voltage (DVDD0, 1, 2): 3.0 to 3.6 V
   Analog power supply voltage (AVDD): 3.0 to 3.6 V
• Speech CODEC:
   G.729.A (8 kbps)/G.711 (64 kbps) µ-law and A-law (supports individual setting for transmission and reception)
   Supports ITU-T G.711 Appendix 1 compliant PLC (Packet Loss Concealment) function
   Supports the 2-channel processing function (for 3-way communication)
• Built-in FIFO buffer (640 bytes) for transmission/reception data transfer
   Allows selection of Frame/DMA (slave) interface
• Echo canceler for handling 32 ms delay
• DTMF detection
• DTMF generation (the tone generation function enables generation of DTMF signals)
• Tone detection: 2 types (1650 Hz and 2100 Hz: Detection frequency can be changed)
• Tone generation: 2 types
• FSK detection
• FSK generation
• Built-in 16-bit timer: 1 channel
• Dial pulse detection function (secondary function of general-purpose I/O ports)
• Dial pulse transmission function (secondary function of general-purpose I/O ports)
• General-purpose I/O ports
   64-pin package: Equipped with 7 ports (with some of them having secondary function allocation)
   100-pin package: Equipped with 21 ports (with some of them having secondary function allocation)
• Two types of built-in linear PCM CODEC (CODEC_A and CODEC_B)
• Analog interface
   CODEC_A side: Incorporates one type each of input amplifier and output amplifier (10 kΩ driving)
   CODEC_B side: Incorporates one type each of input amplifier and output amplifier (10 kΩ driving)
• PCM interface coding format:
   Allows selection of 16-bit linear/G.711 (64 kbps) µ-law or A-law
• PCM serial transmission rate: 64 kHz to 2.048 MHz (fixed to 2.048 MHz for output)
• PCM time slot assignment function (allows up to 2 slots for input and 1 slot for output individually)
   When set to µ-law/A-law: Supports up to 32 slots (BCLK: 2.048 MHz)
   When set to 16-bit linear: Supports up to 16 slots (BCLK: 2.048 MHz)
• Master clock frequency:
   12.288 MHz (crystal; external input)
• Supports hardware and software power down
• Package:
   64-pin plastic QFP (QFP64-P-1414-0.80-BK) (ML7204-001GA)
   100-pin plastic TQFP (TQFP100-P-1414-0.50-BK) (ML7204V-001TB)