Features
• Organization
    - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address
    - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address
• All signals referenced to positive edge of clock, fully synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
    - 143/125/100 MHz
    - 7/8/10 ns clock access time
• Low power consumption
    - Active: 576 mW max
    - Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 32 ms refresh interval
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• PC100 functionality
• Automatic and direct precharge including concurrent autoprecharge
• Burst read, write/Single write
• Random column address assertion in every cycle, pipelined operation
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
    - 400 mil, 44-pin TSOP 2 (2M × 8)
    - 400 mil, 50-pin TSOP 2 (1M × 16)
• Read/write data masking
• Programmable burst length (1/2/4/8/ full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (1/2/3)