General Description
The Microchip USB5926C hub is a low-power, OEM configurable, USB 3.2 Gen 1 hub controller with 6 downstream
ports and advanced features for embedded USB applications. The USB5926C is fully compliant with the Universal Serial
Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5926C supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB downstream
devices on all enabled downstream ports.
The USB5926C supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the
culmination of five generations of Microchip hub controller design and experience with proven reliability, interoperability,
and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 hub controller, decoupling
the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5926C hub feature controller enables OEMs to configure their system using “Configuration Straps.” These
straps simplify the configuration process, assigning default values to USB 3.2 Gen 1 ports and GPIOs. OEMs can disable
ports, enable battery charging, and define GPIO functions as default assignments on power-up, removing the need
for OTP or external SPI ROM.
The USB5926C supports downstream battery charging via the integrated battery charger detection circuitry, which supports
the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5926C provides the
battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
Additionally, the USB5926C includes many powerful and unique features such as:
The Hub Feature Controller, which provides an internal USB device dedicated for use as a USB to I2C/UART/SPI/
GPIO interface, allowing external circuits or devices to be monitored, controlled, or configured via the USB interface.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
Port Split, which allows for the USB3.1 Gen1 and USB2.0 portions of downstream ports 3 and 4 to operate independently
and enumerate two separate devices in parallel in special applications.
USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when
a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC
when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.
The USB5926C can be configured for operation through internal default settings. Custom OEM configurations are supported
through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5926C is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An internal
block diagram of the USB5926C is shown in Figure 2-1.

Highlights
• USB Hub Feature Controller Hub with:
- 2 USB 3.1 Gen 1 USB Type-C® downstream ports
- 2 USB 3.1 Gen 1 legacy downstream ports
- 2 USB 2.0 legacy downstream ports
- USB Type-C upstream port
• USB-IF Battery Charger revision 1.2 support on
up & downstream ports (DCP, CDP, SDP)
• Internal Hub Feature Controller device enables:
- USB to I2C/SPI/GPIO bridge endpoint support
- USB to internal hub register write and read
• USB Link Power Management (LPM) support
• Enhanced OEM configuration options available
through either OTP or SPI ROM
• Supporting latest
Engineering Change Notices for compliance with
USB-IF logo testing for new USB Type-C®
industry initiative (Revision C or newer only)
- Header Packet Timer (TD7.9, TD7.11, TD7.26)
- Power Management Timer (TD7.18, TD7.20, TD7.23)
- Unacknowledged Connect and Remote
Wake Test Failure (TD10.25)
• Available in 100-pin (12mm x 12mm) VQFN
RoHS compliant package
• Commercial and industrial grade temperature
support
Target Applications
• Standalone USB Hubs
• Laptop Docks
• PC Motherboards
• PC Monitor Docks
• Multi-function USB 3.2 Gen 1 Peripherals
Key Benefits
• USB 3.2 Gen 1 compliant 5 Gbps, 480 Mbps,
12 Mbps, and 1.5Mbps operation
- 5V tolerant USB 2.0 pins
- 1.32V tolerant USB 3.2 Gen 1 pins
- Integrated termination and pull-up/down resistors
• Native USB Type-C Support
- Integrated Multiplexer on USB Type-C enabled
ports
- USB 3.1 Gen 1 PHYs are disabled until a valid
USB Type-C attach is detected, saving idle power
• Supports battery charging of most popular battery
powered devices on all ports
- USB-IF Battery Charging rev. 1.2 support
(DCP, CDP, SDP)
- Apple® portable product charger emulation
- Chinese YD/T 1591-2006 charger emulation
- Chinese YD/T 1591-2009 charger emulation
- European Union universal mobile charger support
- Support for Microchip UCS100x family of battery
charging controllers
- Supports additional portable devices
• Smart port controller operation
- Firmware handling of companion port power
controllers
• On-chip microcontroller
- manages I/Os, VBUS, and other signals
• 8 KB RAM, 64 KB ROM
• 8 KB One-Time-Programmable (OTP) ROM
- Includes on-chip charge pump
• Configuration programming via OTP ROM,
SPI ROM, or SMBus
• PortSwap
- Configurable USB 2.0 differential pair signal swap
• PHYBoostTM
- Programmable USB transceiver drive strength for
recovering signal integrity
- USB 2.0 Hi-Speed disconnect threshold adjust
(Revision C or newer only)
• VariSenseTM
- Programmable USB receive sensitivity
• Port Split
- USB2.0 and USB3.1 Gen1 port operation can be
split for custom applications using embedded
USB3.x devices in parallel with USB2.0 devices.
• USB Power Delivery Billboard Device Support
- Internal port can enumerate as a Power Delivery
Billboard device to communicate Power Delivery
Alternate Mode negotiation failure cases to USB
host
• Compatible with Microsoft Windows 10, 8, 7, XP,
Apple OS X 10.4+, and Linux hub drivers
• Optimized for low-power operation and low thermal
dissipation
• Package
- 100-pin VQFN (12mm x 12mm)