Features
■ 32-bit RX CPU core
 32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
 Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
 Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU clock cycle)
 Fast interrupt
 CISC Harvard architecture with five-stage pipeline
 Variable-length instruction format, ultra-compact code
 On-chip debugging circuit
■ Low power consumption functions
 Operation from a single 1.8 to 3.6 V supply
 Three low power consumption modes
 Supply current
High-speed operating mode: 0.11 mA/MHz
Software standby mode: 0.44 μA
 Recovery time from software standby mode: 4.8 μs
■ On-chip flash memory for code, no wait states
 Operation at 32 MHz, read cycle of 31.25 ns
 No wait states for reading at full CPU speed
 16 to 512 Kbyte capacities
 Programmable at 1.8 V
 For instructions and operands
■ On-chip data flash memory
 8 Kbytes
1,000,000 Erase/Write cycles (typ.)
 BGO (Background Operation)
■ On-chip SRAM, no wait states
 8 to 64 Kbyte capacities
■ Data transfer controller (DTC)
 Four transfer modes
 Transfer can be set for each interrupt source.
■ Event link controller (ELC)
 Module operation can be initiated by event signals without
going through interrupts.
 Link operation between modules is possible while the CPU is sleeping.
■ Reset and power supply voltage management
 Six types including Power-On Reset (POR)
 Low voltage detection (LVD) with voltage settings
■ Clock functions
 External clock input frequency: Up to 20 MHz
 Main clock oscillator frequency: 1 to 20 MHz
 Sub-clock oscillator frequency: 32.768 kHz
 PLL circuit input: 4 to 8 MHz
 Low-speed on-chip oscillator: 4 MHz
 High-speed on-chip oscillator: 32 MHz±1% (20 to 85°C)
 IWDT-dedicated on-chip oscillator: 15 kHz
 Generate a dedicated 32.768-kHz clock for the RTC
 On-chip clock frequency accuracy measurement circuit (CAC)
■ Realtime clock (RTC)
 30-second, leap year, and error adjustment functions
 Calendar count mode or binary count mode selectable
 Capable of initiating exit from software standby mode