Features
• AEC-Q100 qualified
• High performance e200z4 triple core:
– 32-bit Power Architecture technology CPU
– Core frequency as high as 180 MHz
– Variable Length Encoding (VLE)
– Floating Point, End-to-End Error Correction
• 6582 KB (6144 KB code flash+ 256 KB data
flash) on-chip flash memory:
– supports read during program and erase
operations, and multiple blocks allowing
EEPROM emulation
– Supports read while read between the two
code Flash partitions.
• 608 KB on-chip general-purpose SRAM (in
addition to 160 KB core local data RAM): 64KB
in CPU_0, 64 KB in CPU_1 and 32 KB in
CPU_2
• 182 KB HSM dedicated flash memory (144 KB
code + 32 KB data)
• Multi-channel direct memory access controller
(eDMA)
– one eDMA with 64 channels
– one eDMA with 32 channels
• 1 interrupt controller (INTC)
• Comprehensive new generation ASIL-D safety
concept:
– ASIL-D of ISO 26262
– One CPU channel in lockstep
– Logic BIST
– FCCU for collection and reaction to failure
notifications
– Memory BIST
– Cyclic redundancy check (CRC) unit
– Memory Error Management Unit (MEMU)
for collection and reporting of error events
in memories
• Crossbar switch architecture for concurrent
access to peripherals, Flash, or RAM from
multiple bus masters with end-to-end ECC
• Body cross triggering unit (BCTU)
– Triggers ADC conversions from any eMIOS
channel
– Triggers ADC conversions from up to 2
dedicated PIT_RTIs
• Enhanced modular IO subsystem (eMIOS): up
to 64 timed IO channels with 16-bit counter
resolution
• Enhanced analog-to-digital converter system
with:
– 4 independent fast 12-bit SAR analog
converters
– One supervisor 12-bit SAR analog
converter
– One standby 10-bit SAR analog converter
• Communication interfaces:
– 18 LINFlexD modules
– 10 deserial serial peripheral interface
(DSPI) modules
– 8 MCAN interfaces with advanced shared
memory scheme and ISO CAN-FD support
– Dual-channel FlexRay controller
– Two independent Ethernet controllers
10/100Mbps compliant IEEE 802.3-2008
• Low power capabilities
– Versatile low power modes
– Ultra low power standby with RTC
– Smart Wake-up Unit for contact monitoring
– Fast wakeup schemes
• Dual phase-locked loops with stable clock domain for peripherals and FM modulation
domain for computational shell
• Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some
support for 2010 standard
• Boot assist Flash (BAF) supports factory programming using a serial bootload through the
asynchronous CAN or LIN/UART
• Junction temperature range -40 °C to 150 °C

Description
The SPC584Gx, SPC58EGx, SPC58NGx microcontroller belongs to a family of devices
superseding the SPC56x family. SPC584Gx, SPC58EGx, SPC58NGx build on the legacy of
the SPC5x family, while introducing new features coupled with higher throughput to provide
substantial reduction of cost per feature and significant power and performance
improvement (MIPS per mW).