Features
HCS12X Core
– 16-bit HCS12X CPU
i. Upward compatible with MC9S12 instruction set
ii. Interrupt stacking and programmer’s model identical to MC9S12
iii. Instruction queue
iv. Enhanced indexed addressing
v. Enhanced instruction set
– EBI (External Bus Interface)
– MMC (Module Mapping Control)
– INT (Interrupt Controller)
– DBG (Debug module to monitor HCS12X CPU and XGATE bus activity)
– BDM (Background Debug Mode)
XGATE (Peripheral Co-Processo)
– Parallel processing module offloads the CPU by providing high speed data processing and
transfer
– Data transfer between Flash EEPROM, RAM, peripheral modules and I/O ports
PIT (Periodic Interrupt Timer)
– Four timers with independent time-out periods
– Time-out periods selectable between 1 and 224 bus clock cycles
CRG (Clock and Reset Generator)
– Low noise/low power pierce oscillator
– PLL
– COP watchdog
– Real time interrupt
– Clock monitor
– Fast wake-up from Stop Mode
8-bit ports with interrupt functionality
– Digital filtering
– Programmable rising or falling edge trigger
Memory
– 512K byte Flash EEPROM
– 4K byte EEPROM
– 32K byte RAM
One 8-channel and one 16 channel Analog-to-Digital Converter
– 10-bit resolution
– External conversion trigger capability
Five 1M bit per second, CAN 2.0 A, B software compatible modules
– Five receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
ECT (Enhanced Capture Timer)
– 16-bit main counter with 7-bit prescaler
– 8 programmable input capture or output compare channels
– Four 8-bit or two 16-bit pulse accumulators
8 PWM channels
– Programmable period and duty cycle
– 8-bit 8-channel or 16-bit 4-channel
– Separate control for each pulse width and duty cycle
– Center-aligned or left-aligned outputs
– Programmable clock select logic with a wide range of frequencies
– Fast emergency shutdown input
– Usable as interrupt inputs
Serial interfaces
– Six asynchronous Serial Communication Interfaces (SCI) with additional LIN support and
selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse width
– Three Synchronous Serial Peripheral Interfaces (SPI)
IIC (Two Inter-IC Bus modules)
– Compatible with IIC Bus standard
– Multi-master operation
– Software programmable for one of 256 different serial clock frequencies
On chip Voltage Regulator
– Two parallel, linear voltage regulators with bandgap reference
– Low Voltage detect (LVD) with Low Voltage Interrupt (LVI)
– Power On Reset (POR) circuit
– 3.3V - 5.5V operation
– Low Voltage Reset (LVR)
– Ultra Low Power Wake-up Timer
144 Pin LQFP, 112-Pin LQFP package and 80-Pin QFP package
– I/O lines with 5V input and drive capability
– Input threshold on external bus interface inputs switchable for 3.3V or 5V operation
– 5V A/D converter inputs
– Operation at 80MHz equivalent to 40MHz bus speed
Development support
– Single-wire background debug™ mode (BDM)
– 4 on-chip hardware breakpoints