Features
 4 Flexible Input Clocks
 One crystal/CMOS input
 Two differential/CMOS inputs
 One single-ended/CMOS input
 Any input frequency from 9.72MHz to 1.25GHz
(300MHz max for CMOS)
 Activity monitors, automatic or manual switching
 Glitchless clock switching by pin or register
 6 or 10 Any-Frequency, Any-Format Outputs
 Any output frequency from 1Hz to 1045MHz
 High-resolution frac-N APLL with 0ppm error
 The APLL has a fractional divider and an
integer divider to make two independent
frequency families
 Output jitter from the integer divider as low as
0.17ps RMS (12kHz-20MHz)
 Output jitter from fractional dividers is typically
< 1ps RMS, many frequencies <0.5ps RMS
 Each output has an independent divider
 Each output configurable as LVDS, LVPECL,
HCSL, 2xCMOS or HSTL
 In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
 Multiple output supply voltage banks with
CMOS output voltages from 1.5V to 3.3V
 Precise output alignment circuitry and peroutput
phase adjustment
 Per-output enable/disable and glitchless
start/stop (stop high or low)
General Features
 Automatic self-configuration at power-up from
external (ZL30260 or 2) or internal (ZL30261 or 3)
EEPROM; up to 8 configurations pin-selectable
 External feedback for zero-delay applications
 Numerically controlled oscillator mode
 Spread-spectrum modulation mode
 Easy-to-configure design requires no external
VCXO or loop filter components
 SPI or I2C processor Interface
 Core supply voltage options: 2.5V only, 3.3V
only, 1.8V+2.5V or 1.8V+3.3V
 Space-saving 8x8mm QFN56 (0.5mm pitch)
 Easy-to-use evaluation/programming software
Applications
Frequency conversion and frequency synthesis in
a wide variety of equipment types