1.2 Features
♦ Universal Serial Bus Specification Revision 2.0 compliant
♦ Built-in USB transceiver
♦ Supports both Hi-Speed (480M bps) and Full-Speed (12M bps)
♦ USB protocol layer by hardware
• Bit stuffing encoding and decoding
• CRC (Cyclic Redundancy Check) generation and checking
• NRZI (Non Return Zero Invert) encoding and decoding
• Packet detection
• USB address checking
♦ Hi-Speed and Full-Speed detection by hardware
♦ Supports the following USB transfer types
• Control transfer (PIPE0)
• Bulk transfer (PIPE1~PIPE4)
• Interrupt transfer (PIPE5~PIPE6)
♦ Built-in FIFO buffer (3.5K bytes) for endpoints
♦ Up to 7 endpoints selectable
♦ Data transfer condition selectable for each PIPE
• Hi-Speed
- PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO
- PIPE1~2: Bulk in or bulk out transfer, 512-byte FIFO, double buffer
- PIPE3~4: Bulk in or bulk out transfer, 512-byte FIFO, single buffer
- PIPE5~6: Interrupt in transfer, 64-byte FIFO, single buffer
• Full-Speed
- PIPE0: Control transfer, continuous transfer mode, 256-byte FIFO
- PIPE1~2: Bulk in or bulk out transfer, continuous transfer mode, 512-byte FIFO, double buffer
- PIPE3~4: Bulk in or bulk out transfer, continuous transfer mode, 512-byte FIFO, single buffer
- PIPE5~6: Interrupt in transfer, 64-byte FIFO, single buffer
♦ Automatic response for Set Address request
♦ Supports the following input frequency
• 12 / 24 / 48MHz
♦ Supports 16-bit CPU I/F and 8/16-bit DMA transfer
♦ Supports separate/multiplex bus
• 16-bit separate/multiplex bus
♦ Supports 8-bit split bus (DMA interface)
♦ USB status output for power management
♦ 1.8V/3.3V interface power supply