Features
Features of the MC68HC705MC4 are listed below. Note that all timing is
based on a 3-MHz bus.
• Low-Cost, HC05 Core Running at 3-MHz Bus Speed at VDD = 5 V
± 10%
• 28-Pin Plastic Dual In-Line Package (PDIP), Small Outline
Integrated Circuit (SOIC), or Windowed Ceramic Package with
Low Electromagnetic Interference (EMI) Emission Pinout
• 3584 Bytes of User EPROM, Including Eight User Vectors of Two
Bytes Each
• 176 Bytes of User RAM
• Dual-Channel, High-Speed PWM, Featuring:
– 8-Bit Duty Cycle Resolution
– Independent Prescaler Frequency Selection and Period
Counters
– Two Frequency Ranges, Eight Steps in Each:
183 Hz to 23.4 kHz
122 Hz to 15.6 kHz
– Software Programmable PWM Polarity
– Dual Software Controllable PWM Output Multiplexer, Each
PWM to Three Input/Output (I/O)
• 8-Bit A/D Converter with Six Input Multiplexer
– High and Low References
– Conversion Rate = 10.7 ms
• 16-Bit Timer with Two Input Captures or One Input Capture Plus
One Output Compare
– Resolution = 1.33 ms
– Input Capture Active Edge Software Selectable as Rising or
Falling
• 15-Stage, Multi-Function Core Timer with Timer Overflow,
Real-Time Interrupt, and Watchdog
• Asynchronous Serial Communications Interface (SCI)
• 22 General-Purpose I/O Lines, Some Shared with Peripheral
Functions
• One 8-Bit High Source Current I/O Port
– 10 mA/Pin
– 20 mA Maximum/Port
– Port A
• One High-Sink Current 10 mA Output Pin, PB7
• Mask, Request, Acknowledge, Edge and Sensitivity (Edge- and
Level-Sensitive or Edge-Sensitive Only) Control/Status Bits for
IRQ Interrupt
• On-Chip Oscillator for Crystal/Ceramic Resonator
• Mask Selectable Computer Operating Properly (COP) Watchdog
System
• Illegal Address Reset
• Steering Diode on RESET Pin to VDD