1 General description
The PCAL9714 is a 14-bit general purpose I/O expander that provides remote I/O expansion for most
microcontroller families via the Serial Peripheral Interface (SPI). The ultra low-voltage interface allows for direct
connection with the microcontroller operating down to 1.1 V.
NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections
to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running
at one voltage level down to 1.1 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. The
PCAL9714 has built-in level shifting feature that makes these devices extremely flexible in mixed power
supply systems where communication between incompatible I/O voltages is required, allowing seamless
communications with next-generation low voltage microprocessors and microcontrollers on the interface side
and peripherals at a higher voltage on the port side.
There are two supply voltages for PCAL9714: VDD(SPI) and VDD(P). VDD(SPI) provides the supply voltage for the
interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core circuits
and Port P. The bidirectional voltage level translation in the PCAL9714 is provided through VDD(SPI). VDD(SPI)
should be connected to the VDD of the external SPI interface lines. This indicates the VDD level of the SPI to the
PCAL9714, while the voltage level on Port P of the PCAL9714 is determined by the VDD(P).
The PCAL9714 works with the SPI speed at 5 MHz and implements Agile I/O, which are additional features
specifically designed to enhance the I/O. These additional features are: programmable output drive strength,
latchable inputs, programmable pullup/pulldown resistors, maskable interrupt, interrupt status register,
programmable open-drain or push-pull outputs.
Additional Agile I/O Plus features include interrupts specified by level or edge, and they can be cleared
individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented.
At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity
Inversion register, saving external logic gates. Programmable pullup and pulldown resistors eliminate the need
for discrete components.
The system master can reset the PCAL9714 in the event of a time-out or other improper operation by asserting
a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the SPI
state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
The PCAL9714 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
(INT) can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the
remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate
via the SPI. Thus, the PCAL9714 can remain a simple slave device. The input latch feature holds or latches the
input pin state and keeps the logic values that created the interrupt until the master can service the interrupt.
This minimizes the host’s interrupt service response for fast moving inputs.
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device
current.
One hardware pin (ADDR) can be used to program and vary the fixed SPI-bus address and allow up to four
devices to share the same SPI bus.

2 Features and benefits
• SPI bus to parallel port expander
• 5 MHz SPI bus
• Operating power supply voltage range of 1.1 V to 5.5 V on the SPI bus side
• Allows bidirectional voltage-level translation and GPIO expansion between 1.1 V to 5.5 V on SPI and 1.8 V,
2.5 V, 3.3 V or 5.5 V Port P
• Low standby current consumption: 2.0 μA typical at 3.3 V VDD
• 5.5 V tolerant I/O ports and SPI bus pins
• Active LOW reset input (RESET)
• Open-drain active LOW interrupt output (INT)
• Internal power-on reset
• Power-up with all channels configured as inputs
• No glitch on power-up
• Latched outputs with 25 mA drive maximum capability for directly driving LEDs
• Latch-up performance exceeds 100 mA per JESD 78, Class II
• ESD protection exceeds JESD 22
– 2000 V Human-Body Model (A114-A)
– 1000 V Charged-Device Model (C101)
• Package offered: HVQFN24

2.1 Agile I/O features
• Output port configuration: bank selectable push-pull or open-drain output stages
• Interrupt status: read-only register identifies the source of an interrupt
• Bit-wise I/O programming features:
– Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance
applications
– Input latch: Input Port register values changes are kept until the Input Port register is read
– Pullup/pulldown enable: floating input or pullup/pulldown resistor enable
– Pullup/pulldown selection: 100 kΩ pullup/pulldown resistor selection
– Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts

2.2 Additional Agile I/O Plus features
• Interrupt edge specification on a bit-by-bit basis
• Interrupt individual clear without disturbing other events
• Read all interrupt events without clear
• Switch debounce hardware