Features

High-performance embedded RISControllerTM
microprocessor, based on IDT RISCore32300TM 32-bit CPU
core
– Based on MIPS 32 RISC architecture with enhancements
– Scalar 5-stage pipeline minimizes branch and load delays
– 66 Million multiply accumulate (MAC) Mul-Add/second
@ 133MHz
– 100 and 133 frequencies

MIPS 32 (ISA) instruction set architecture
– MIPS IV compatible conditional move instructions
– MIPS IV superset PREF (prefetch) instruction
– Fast multiplier with atomic multiply-add, multiply-sub
– Count leading zeros/ones instructions

Large, efficient on-chip caches
– Separate 8kB Instruction cache and 2kB Data cache
– 2-way set associative
– Write-back and write-through support on a per page basis
– Optional cache locking with “per line” resolution, to facilitate
deterministic response
– Simultaneous instruction and data fetch in each clock cycle,
sustained rate, achieves over 1 GB/sec bandwidth