1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with 3-state
outputs that enable bidirectional level translation. They feature two 2-bits input-output ports
(nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable
for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V).
Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR
allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and
B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid logic
level.
2. Features and benefits
• Wide supply voltage range:
• VCC(A): 1.2 V to 5.5 V
• VCC(B): 1.2 V to 5.5 V
• High noise immunity
• Complies with JEDEC standards:
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM JESD22-A114F Class 3A exceeds 4000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Maximum data rates:
• 420 Mbps (3.3 V to 5.0 V translation)
• 210 Mbps (translate to 3.3 V))
• 140 Mbps (translate to 2.5 V)
• 75 Mbps (translate to 1.8 V)
• 60 Mbps (translate to 1.5 V)
• Suspend mode
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• ±24 mA output drive (VCC = 3.0 V)
• Inputs accept voltages up to 5.5 V
• Low power consumption: 16 μA maximum ICC
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C