1. General description
The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data
inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset
(MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold
time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear
at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include
clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
• Input levels:
• For 74HC175: CMOS level
• For 74HCT175: TTL level
• Four edge-triggered D-type flip-flops
• Asynchronous master reset
• Complies with JEDEC standard no. 7A
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C.