1. General description
The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features
clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their
corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
clock (CP) transition. Input E must be stable one set-up time prior to the LOW-to-HIGH transition
for predictable operation. Inputs include clamp diodes that enable the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• Input levels:
• For 74HC377: CMOS level
• For 74HCT377: TTL level
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V.
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C