FEATURES
· 300 outputs
· CMOS level input
· Input of 6 bits (gradation data) by 6 dots
· Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
· Output dynamic range : VSS2+0.1 V to VDD2-0.1 V
· Logic part supply voltage (VDD1) : 3.3 V ± 0.3 V
· Driver part supply voltage (VDD2) : 8.0 V ± 0.5 V
· High-speed data transfer: fMAX=40 MHz MIN.(internal data transfer rate when operating at 3.0 V)
· Output voltage polarity inversion is possible (POL)
· Display data inversion function (POL2)
· Single bank arrangement is possible(loaded with slim TCP).