FEATURES
• CMOS level input
• 402/384 outputs
• 6 bits (gray scale data) x 3 dots input
• 64-value output by 10 external power supplies and internal D/A converter
• Output dynamic range: VSS2 + 0.1 V to VDD2 − 0.1 V
• High-speed data transfer: fCLK = 50 MHz MAX. (internal data transfer rate at supply voltage VDD1 of logic circuit = 3.0 V)
• Level of γ -corrected power supply can be inverted
• Precharge-less output buffer
• Input data inversion function (INV)
• Logic supply voltage (VDD1): 3.3 V ± 0.3 V
• Driver supply voltage (VDD2): 5.0 V ± 0.5 V
• Slim TCP
• Current consumption reduction function (Bcont)