FEATURES
• FUNCTIONS
• Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 60, 30, 20, 15, 7.5 MHz
Crystal: 60 MHz
• On-chip PLL to provide higher operation clock than the external clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
• PROGRAMMING
• 16 bits ´ 16 bits + 40 bits ® 40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L*R2L)
• Nonpipeline on execution stage
• MEMORY AREAS
• Instruction memory area : 64K words ´ 32 bits
• Data memory areas : 64K words ´ 16 bits ´ 2 (X memory, Y memory)