Features
The features listed below which may or may not be present in actual product, may be subject to the third-party licensing requirements. Please contact Rockchip for actual product feature configurations and licensing requirements.
1.2.1 Microprocessor
 Quad-core ARM Cortex-A53 CPU
 Full implementation of the ARM architecture v8-A instruction set
 ARM Neon Advanced SIMD (single instruction, multiple data) support for accelerated media and signal processing computation
 ARMv8 Cryptography Extensions
 In-order pipeline with symmetric dual-issue of most instructions
 Unified system L2 cache
 Include VFP v3 hardware to support single and double-precision operations
 Integrated 32KB L1 instruction cache, 32KB L1 data cache with 4-way set associative
 TrustZone technology support
 Full CoreSight debug solution
 One separate power domains for CPU core system to support internal power switch and externally turn on/off based on different application scenario
 PD_A53: Cortex-A53 + Neon + FPU + L1 I/D Cache of core 2/3
 One isolated voltage domain to support DVFS
1.2.2 Memory Organization
 Internal on-chip memory
 BootROM
 Internal SRAM
 External off-chip memory①
 DDR3/DDR3L/LPDDR3/DDR4
 SPI Flash
 eMMC
 SD
1.2.3 Internal Memory
 Internal BootRom
 Support system boot from the following device:
 SPI Flash interface
 eMMC interface
 SDMMC interface (SDMMC0 only)