OVERVIEW

The ZSP540 processor core is a high-performance/power-efficient QuadMAC/Six-ALU implementation of the ZSP®G2 architecture. The ZSP540 utilizes a 16-bit architecture with extensive 32-bit capabilities and sets an unmatched balance of performance/power/size and memory utilization efficiency. The Z.Turbo feature provides the SOC designer with the option to extend the ZSP540 Instruction Set and the ability to add application-specific acceleration logic.

CORE FEATURES

• Quad-MAC/Six-ALU DSP core

• 4+1 instructions per cycle

• Up to 350MHz, 8-stage pipeline design

• Up to 1750 million instructions/sec

• Dual 64-bit wide Load/Store data ports

• Z.Turbo coprocessor extensions capable

• 24-bit address space

• HW managed instructions scheduling

• HW/SW controlled power management

• Real-time trace and profiling capability

• Full AMBA/AHB support (optional)

• JTAG debug interface

• Static, single phase clocked design

• Compatible with all other ZSP cores

ARCHITECTURE FEATURES

• Embedded control processing efficiency

• 32-bit addressing capabilities

• 16 and 32-bit standard instruction set

• Extensive 32-bit and 40-bit support

• Easy to program instruction set

• Load/store register based instructions

• Outstanding code density

• User extensible instruction set

APPLICATION BENEFITS

•High-performance DSP capabilities

•Excellent power/cost/speed balance

•Excellent multimedia audio/video processing

•Power efficient baseband processing performance

•DSP and system control functions handling capabilities

CORE FEATURES

• Quad-MAC/Six-ALU DSP core

• 4+1 instructions per cycle

• Up to 350MHz, 8-stage pipeline design

• Up to 1750 million instructions/sec

• Dual 64-bit wide Load/Store data ports

• Z.Turbo coprocessor extensions capable

• 24-bit address space

• HW managed instructions scheduling

• HW/SW controlled power management

• Real-time trace and profiling capability

• Full AMBA/AHB support (optional)

• JTAG debug interface

• Static, single phase clocked design

• Compatible with all other ZSP cores

ARCHITECTURE FEATURES

• Embedded control processing efficiency

• 32-bit addressing capabilities

• 16 and 32-bit standard instruction set

• Extensive 32-bit and 40-bit support