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SAA7112 数据表 (PDF) - NXP Semiconductors

SAA7112 Datasheet PDF - NXP Semiconductors
部件名 SAA7112
下载  SAA7112 下载
文件大小   81.57 Kbytes
  8 Pages
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors
功能描述 Decoder with High-Performance Scaler HPS for Image Port PELICAN

SAA7112 Datasheet (PDF)

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SAA7112 Datasheet PDF - NXP Semiconductors

部件名 SAA7112
下载  SAA7112 Click to download

文件大小   81.57 Kbytes
  8 Pages
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors
功能描述 Decoder with High-Performance Scaler HPS for Image Port PELICAN

SAA7112 数据表 (HTML) - NXP Semiconductors


SAA7112 产品详情

GENERAL DESCRIPTION

The PELICAN SAA7112 is a video capture device for applications at the image port of VGA controllers.

The SAA7112 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multistandard decoder and a SAA7140B based scaler, including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit (see Fig.1).



FEATURES

The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights:

Video Decoder

• Six analog inputs, internal analog source selectors, (e.g. 6 × CVBS or(2 × YC and 2 × CVBS) or (1 × YC and 4 × CVBS)

• Two analog preprocessing channels, including built in analog anti-alias filters

• Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel

• Two 8 bit video CMOS Analog-to-Digital Converters (ADCs)

• Automatic Clamp Control (ACC) for CVBS, Y and C

• Switchable white peak control

• On-chip line locked clock generation in accordance with CCIR-601

• Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR

• Requires only one crystal (32.11 MHz) for all standards

• Horizontal and vertical sync detection

• Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC

• Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM

• User programmable luminance peaking or aperture correction

• Cross-colour reduction for NTSC by chrominance combination filtering

• PAL delay line for correcting PAL phase errors

• Real time status information output (RTCO)

• Independent Brightness Contrast Saturation (BCS) adjustment for decoder part.



Video Scaler

• Horizontal and vertical down-scaling and up-scaling to randomly sized windows

• Horizontal and vertical scaling range: 2 (zoom) to 1⁄64 (icon); vertical zoom might be restricted

• Anti-alias- and accumulating filter for horizontal scaling

• Vertical scaling with linear phase interpolation (6-bit phase accuracy) and accumulating filter for anti-aliasing

• Horizontal phase correct up- and down-scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy

• Two independent programming sets for scaler part, to define two ‘ranges’ per field or per frame

• Field-wise switching between decoder-part and expansion port input

• Brightness, contrast and saturation controls for scaled outputs.



VBI-data decoder and text slicer

• versatile VBI-data decoder, slicer, clock regeneration and byte synchronization; e.g. for WST, NABST, Close Caption, WSS, etc.



Audio clock generation

• Generation of a field locked audio master clock to support a constant number of audio clocks per video field

• Generation of an audio serial and left/right (channel) clock signal.



Digital I/O interfaces

• Real time signal port (R-port), including continuous line locked reference clock and real time status information

• Bidirectional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV

   – output from decoder part, real time, or

   – input to scaler part, e.g. video from MPEG-decoder

• Video image port (I-port) configurable for 8-bit (16-bit) data in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals

• 8-bit data Host port (H-port) for 16-bit extension of I-port

• Discontinuous data streams supported

• 32-word × 4 bytes FIFO register for video output data

• 16-word × 4 bytes FIFO register for decoded VBI output data Scaled 4 : 2 : 2, 4 : 1 : 1 YUV output

• Scaled 8-bit luminance only and raw data output

• Decoded VBI data output.



 




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关于 NXP Semiconductors


NXP半导体是一家公开交易的跨国公司,设计,开发和制造各种半导体和集成电路,用于各种应用,包括汽车,工业,通信和消费市场。
该公司成立于2006年,总部位于荷兰的埃因霍温。
NXP提供了广泛的产品组合,包括微控制器,微处理器,安全身份验证IC,电源管理ICS,RF和微波炉组件以及传感器解决方案等。
该公司的产品旨在具有节能,安全和可靠,并用于各种应用中,包括汽车系统,工业自动化和控制,智能家居和建筑物以及连接的设备。
NXP致力于创新和客户满意度,并致力于为客户提供最佳的半导体解决方案,以满足他们的需求。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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