GENERAL DESCRIPTION
The TDA10085 is a single-chip channel receiver for satellite television reception matching both DSS and DVB-S standards. The device contains a dual 6-bit flash ADC, variable rate BPSK/QPSK coherent demodulator and forward error correction functions. The ADC interfaces directly with I and Q analog baseband signals.

FEATURES
• DSS and DVB-S compliant single chip demodulator and forward error correction
• Dual 6-bit Analog-to-Digital Converter (ADC) on-chip
• PLL that allows using a low-cost crystal (typically 4 MHz)
• DiSEqC 1.X from 1 to 8 byte-long sequences with modulated or unmodulated output
• DSS dish control
• Digital cancellation of ADC offset
• Simultaneous parallel and serial output interfaces
• Variable rate BPSK/QPSK coherent demodulator
• Modulation rate variable from 1 to 49 Mbauds
• Automatic gain control output
• Digital symbol timing recovery:
    – Acquisition range up to 960 ppm
• Carrier offset cancellation up to one half of the sampling frequency
• Digital carrier recovery:
    – Acquisition range up to 12% of the symbol rate
• Half-Nyquist filters: roll-off = 0.35 for DVB and 0.2 for DSS
• Interpolating and anti-aliasing filters to handle variable symbol rates
• Channel quality estimation
• Spectral inversion ambiguity resolution
• Viterbi decoder:
    – Supported rates from 1/2 to 8/9
    – Constraint length K = 7 with G1 = 1718 and G2 = 1338
    – Viterbi output BER measurement
    – Automatic code rate search within 1/2, 2/3 and 6/7 in DSS mode
    – Automatic code rate search within 1/2, 2/3, 3/4, 5/6 and 7/8 in DVB-S mode
• Convolutional de-interleaver and Reed Solomon decoder according to DVB and DSS specifications
• Automatic frame synchronization
• Selectable DVB-S descrambling
• I2C-bus interface
• 64-pin TQFP package
• CMOS technology (0.2 µm, 1.8 V to 3.3 V)

APPLICATIONS
• DVB-S receivers (ETS 300-421)
• DSS receivers.