KEY FEATURES
 Port and Lane Configurations for 12-port/24-Lane PCI Express GEN3 packet switch
。 Configurable Upstream port number up to 2
。 Configurable Upstream lane widths of x1, x2, x4 or x8
。 Configurable Downstream port number up to 11
。 Configurable Downstream lane widths of x1, x2, x4 or x8
 Reference Clock Management
。 Integrated PCIe Gen3 clock buffer for all downstream ports
。 Support three reference clock structures (Common, SRNS and SRIS)
。 Handle SSC Isolation up to three ports
。 Provide two clock application modes (Base and CDSR)
 Power Management
。 Support 7 power states (P0/P0s/P1/P1.1/P1.2/P2/P1.2PG)
。 Start-up power management scheme
- “Empty” Hot-Plug ports put in P2 state
 PHY and MAC Layers
。 PHY initial settings optionally programmable through JTAG, EEPROM, and SMBus/I2C
。 Adaptive Continuous Time Linear Equalizer and 5-tap Decision Feedback Equalizer for RX
。 Adaptive and programmable 3-tap TX equalization
。 RX Polarity Inversion and Lane Reversal
 Data Link Layer
。 Programmable ACK latency timer to respond ACK based upon traffic condition
。 Configurable Flow Control Credit to balance bandwidth utilization and buffer usage
 Transaction Layer
。 Packet forwarding options including Cut-Through and Store & Forward
。 Support up to 512-Byte Max Payload Size
。 Low packet forwarding latency < 150ns (typical case)
。 Access Control Service (ACS) for peer-to-peer traffic
。 Address Translation (AT) packet for SR-IOV application
。 Support Atomic operation
。 Support Multicast
。 Provide Performance Visibility for ingress/egress packet types and packet counts
 Multi-Host Application
。 Support up to 3 Cross-Domain End-Point (CDEP) ports for Host-to-Host Communications
。 Support Fail-over using CDEP port
。 Provide up to 8 physical or 16 virtual DMA channels enabling communications among Hosts and EPs
。 Switch bifurcated up to 2 individual packet switches to allow 2 hosts operating independently
 Reliability, Availability and Serviceability
。 Enhanced Advanced Error Reporting
。 End-to-End Data Protection with ECC
。 Error Handling Mechanism
。 Support Surprise Hot Removal
。 Support Downstream Port Containment (DPC)
。 Support Hot Plug for Upstream and Downstream port
。 Provide Serial and Parallel Hot Plug Types
。 Support LED Management
。 Thermal Sensor reporting operational temperature instantly
。 IEEE 1149.1 and 1149.6 JTAG interface support
 Advanced Diagnostic Tools
。 PHY EyeTM
。 MAC ViewerTM (including embedded LA and LTSSM monitor)
。 PCIBUDDYTM
。 On-the-fly PRBS loopback test
。 On-the-fly Compliance pattern test
 Side-band Management Interface
。 I2C/SMBUS/JTAG
。 SPI EEPROM
 Standard Compliance
。 Compliant with PCI Express Base Specification Revision 3.1
。 Compliant with PCI Express CEM Specification Revision 3.0
。 Compliant with Advanced Configuration Power Interface (ACPI) Specification
。 Compliant with System Management (SM) Bus, Version 2.0
 Power & Package
。 Two power rails (0.95V and 1.8V)
。 Power consumption: 5.33W (Note 1)
。 Totally Lead-Free & Fully RoHS Compliant (Notes 2 & 3)
。 Halogen and Antimony Free. “Green” Device (Note 4)
。 For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP
capable, and manufactured in IATF 16949 certified facilities), please contact us or your local Diodes representative.
https://www.diodes.com/quality/product-definitions/
。 Packages: 324 HFCBGA 19mm x 19mm
 Operating Ambient Temperature
。 Support Industrial Temperature Range -40o
to 85
oC (Note 5)

GENERAL DESCRIPTION
Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the basic function of PCI Express (PCIe) Switch is to
expand the connectivity to allow more end devices being reached by host controllers in terms of PCIe serial interconnect
architecture. This 24-lane and 12-port PCIe Switch can extend the connections ranged from 3 to 12 PCIe devices by means of
its flexible port and lane configurations. It provides users the variety to expand or fan-out the PCI Express lanes from one
host based upon their application needs.
In PCI Express system bus hierarchy, the packet switch can be visualized as a logical assembly of multiple virtual PCI-to-PCI
Bridge (PPB), which represents either upstream or downstream port. Also, normally all of the primary buses of downstream
ports and secondary bus of upstream port are shared with one common virtual PCI Bus. In terms of the port configuration
setting in a single host environment, the packet switch PI7C3G1224GP, which is constructed with 2 tiles, can be enumerated
with one upstream-port PPB and up to 7 downstream-port PPBs in Tile 1 and 4 downstream-port PPBs in Tile 2. Then, the
switch can be further discovered in another tile with one additional virtual downstream-port PPB cascaded with one virtual
upstream-port PPB and up to 4 additional downstream-port PPBs under the virtual upstream-port PPB. Alternatively, in
Switch Partition Mode, PI7C3G1224GP can be viewed as two independent PCI bus hierarchies in two different host domains.
In Tile 0, bus hierarchy contains one upstream-port PPB and up to 7 downstream-port PPB’s. In Tile 1, bus hierarchy
contains one upstream-port PPB and up to 3 downstream-port PPB’s.
The chip adopts hybrid architecture of Multiple-Ring and Network-on-Chip (NOC) as a switch core for reaching each
individual port. There are 8 physical ports attached to one multiple-ring, which is a basic cell of switch architecture, called a
tile. Two tiles are connected to each other through NOC to expand into a 12-port packet switch. Each port employs the
structure of Combined Input and Output Queue (CIOQ) for buffer management. The main reason for choosing CIOQ is that
the required memory bandwidth of input queue equals the line rate of ingress port rather than increasing proportionally with
port numbers as is the case of an output queue Switch. The CIOQ at each ingress port contains separate dedicated input
queues to store posted data, non-posted requests and completion packets. The packets are arbitrated to the egress port based
upon the ID or address carried in the packet header along with the PCIe transaction-ordering rules.
Packets can be forwarded in downstream, upstream or peer-to-peer direction concurrently. For the packets without ordering
enforcement, they are permitted to pass over each other in cases where the addressed egress port is available to accept them.
This can mitigate the issue of Head-Of-Line (HOL) blocking and also not affecting the operation of producer-consumer
model, which is required to be retained to prevent from system hang-up problem. On the other hand, the replay buffer at each
egress port (output queue) enhances data integrity by preserving the transmitted packets until the appropriate ACK is returned
by the link partner. As the out-going packets can be stored in replay buffer,this can gain the maximum throughput and
efficiency of the Switch. Another advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the
counterpart is simplified and streamlined in terms of the credit-based flow control protocol. The protocol requires that each
ingress port maintains the credits independently without checking other ports' credit availability, which is otherwise required
by pure output queue architecture.
The Switch supports several advanced features of latest PCI Express specification. They include Access Control Service
(ACS), Multi-Cast, Atomic Operation, Alternate Routing ID (ARI) and Address Translation (AT) packet forwarding etc.
ACS allows the host system to have more control on peer-to-peer switch traffic. This can be a critical requirement in virtual
machine system. Multi-Cast is an extended capability of PCIe switch to facilitate posted packets forwarded to a group of
downstream ports efficiently. The switch is also capable of being a routing element for Atomic Operation commands, which
has the advantages of synchronization among multiple processors or multiple-thread environment. When ARI capability is
turned on, the ID routing has an alternative interpretation on Device and Function numbers. The Function number can be
increased from 3 bits to 8 bits. This allows the downstream port of packet switch forwarding packets with up to 256
Functions.
Up to three dedicated ports in PI7C9X3G1224GP can be programed as Cross-Domain End Point (CDEP) ports to support
packet forwarding among multiple hosts and end-point devices. When the port is in CDEP mode (i.e. CD port for
abbreviation), it would isolate the address and ID spaces of one host from another host. If the packet issued from one host
domain to another host domain passes through CD port, the packet switch will be responsible for translating address and ID
of packets in order to prevent resource conflicts among domains. Meanwhile, the CD port also provides several mechanisms
to facilitate inter-processor communication. CDEP mode is configured by EEPROM programming after power up.
PI7C9X3G1224GP supports embedded Direct Memory Access (DMA) capability to move data between two address
locations that are set up via DMA channels. There are eight physical DMA channels implemented in PI7C9X3G1224GP and
each physical channel can be shared by two virtual channels. So a total of 16 DMA channels can be enabled in the packet
switch to allow 16 pairs of locations transferring data simultaneously. The DMA engine is configured and managed by a
software driver running on the hosts connected to the upstream port or CD ports. In terms of the address locations and DMA
ownership, the DMA engines can be used in a variety of applications such as device status collection, peer-to-peer host
transfer and peer-to-peer end-point transfer etc.