Features
The features listed below which may or may not be present in actual product, may be
subject to the third party licensing requirements. Please contact Rockchip for actual product
feature configurations and licensing requirements.

Video input interface
 HDMI RX interface
 Compliant with HDMI 1.4/HDMI 2.0
 Supports 8/10bit per component video format
 Supports rgb888/yuv420
 Supports Max resolution 4k@60fps (yuv420)
 Supports DDC Bus I2C master interface at 3.3/5V
 Supports EDID and CEC function
 Parallel RX interface
 Supports Max resolution 1080p@60fps
 Supports 16bits BT.1120 in
 Supports 24bits parallel RGB in

Video output interface
 HDMI TX interface
 Supports all DTV resolutions including 720p /1080p
 Supports data rate from 25MHz, 1.65bps up to 3.4Gbps over a Single channel
HDMI Internal SRAM
 TMDS Tx Drivers with programmable output swing, resister values and preemphasis
 DDC Bus I2C master interface at 3.3/5V
 The EDID and CEC function are also supported by HDMI Transmitter Controller
 MIPI TX interface
 DSI
 Compliant with MIPI DPHY V1.2
 Support the DPI interface color coding mappings into 24-bit Interface
 Up to 4 DPHY Data Lanes per channel
 Supports data rate up to 1.2Gbps
 Supports dual channel ,DSI0 and DSI1
 CSI
 Compliant with MIPI DPHY V1.2
 Support format: YUV422
 Up to 4 DPHY Data Lanes
 Supports data rate up to 1.2Gbps
 Supports single channel ,combine with DSI0
 GVI TX interface
 Supports RGB666/RGB888/RGB101010/YCbCR422-8bit/YCBCR422-10bit format
 Supports Max resolution 4k@60fps
 Supports up to 3.75Gbps data rate(effective data rate 3Gbps)
 Supports 1/2/4/8 lanes
 Supports output lanes flexible mapping
 Supports 1/2 section mode
 LVDS TX interface
 Compliant with the Standard TIA/EIA-644-A LVDS standard
 Supports data rate up to 1Gbps
 Support 8bit format-1, format-2, format-3 display mode, Support 6bit display
mode.
 Supports dual channel LVDS
 Parallel TX interface
 Supports Max resolution 1080p@60fps
 Supports 16bits BT.1120 out
 Supports 24bits parallel RGB out

Post process
 CSC
 RGB2YUV
 YUV2RGB
 YUV2VYU
 Display interface
 Parallel display Interface: 30-bit(RGB/YUV)
 Asynchronous output pixel clock (PLL required)
 Flexible display timing setting
 Configurable border black area
 Scaling down
 Max input resolution: 4096x2160
 Arbitrary non-integer scaling ratio
 Support two mode: bilinear and average
 Max 1/4 scaling ratio for bilinear scaling down
 Max 1/6 scaling ratio for average scaling down
 Scaling up
 Max output resolution: 4096x2160
 Arbitrary non-integer scaling ratio
 Support four scaling up mode for different effect
 Max 6 scaling ratio
 Split
 Left-right mode
 Odd-even mode(LVDS only)