Description
The PM6344 Quadruple E1 Framer (EQUAD) is a feature-rich device suitable for use in many E1 systems with a minimum of external circuitry. Each of the framers and transmitters is independently software configurable, allowing feature selection without changes to external wiring.
On the receive side, the EQUAD recovers clock and data and can be configured to frame to a basic G.704 2048 kbit/s signal or also frame to the signaling multiframe alignment signal and the CRC multiframe alignment signal.

FEATURES
• Integrates four full-featured E1 framers and transmitters in a single device for terminating duplex E1 signals.
• Software and functionally compatible with the PM6341 E1XC Single E1 Transceiver.
• Pin compatible with the PM4344 Quad T1 Framer device.
• Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power CMOS technology
• Available in a 128 pin PQFP package.

Each one of four receiver sections:
• Recovers clock and data using a digital phase locked loop for high jitter tolerance. A direct clock input is provided to allow clock recovery to be bypassed.
• Accepts dual rail or single rail digital PCM inputs.
• Supports HDB3 or AMI line code.
• Accepts gapped data streams to support higher rate demultiplexing.
• Frames to a G.704 2048 kbit/s signal within 1 ms.
• Frames to the signaling multiframe alignment when enabled.
• Frames to the CRC multiframe alignment when enabled.
• Provides loss of signal detection, and indicates loss of frame alignment (OOF), loss of signaling multiframe alignment and loss of CRC multiframe alignment.
• Supports line and path performance monitoring according to ITU-T recommendations. Accumulators are provided for counting:
• CRC-4 errors to 1000 per second;
   Far end block errors to 1000 per second;
   Frame sync errors to 127 per second; and
   Line code violations to 8191 per second.
• Indicates the reception of remote alarm and remote multiframe alarm.
• Indicates the reception of alarm indication signal (AIS) and time slot 16 AIS.
• Declares RED and AIS alarms using Q.516 recommended integration periods.
• Provides an HDLC/LAPD interface for terminating a data link. Supports polled, interrupt-driven, or DMA servicing of the HDLC interface.
• Optionally extracts the data link from timeslot 16 (64 kbit/s), which may be used to receive common channel signaling, or from any combination of the national bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).
• Supports fractional E1 channel extraction.
• Provides a two-frame elastic store buffer for jitter and wander attenuation that performs controlled slips and indicates slip occurrence and direction.
• Provides channel associated signaling extraction, with optional data inversion, programmable idle code substitution, and up to 3 multiframes of signaling debounce on a per-timeslot basis.
• Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all timeslots or on selected timeslots.
• Optionally provides dual rail digital PCM output signals to allow BPV transparency. Also supports unframed mode.
• Supports transfer of PCM and signaling data to 2.048 Mbit/s or 16.384Mbit/s backplane buses.
• Can be configured to attenuate jitter on the receive side by placing the digital jitter attenuator in the receive path.

APPLICATIONS
• E1 Channel Service Units (CSU) and Data Service Units (DSU)
• E1 Channel Banks and Multiplexers
• Digital Private Branch Exchanges (PBX)
• Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX)
• E1 Frame Relay Interfaces
• E1 ATM Interfaces
• ISDN Primary Rate Interfaces (PRI)
• SDH Byte Synchronous TU12 Mappers
• Test Equipment