DESCRIPTION
The PM7326 S/UNI APEX is a full duplex ATM traffic management device, providing cell switching, per VC queuing, traffic shaping, congestion management, and hierarchical scheduling to up to 2048 loop ports and up to 4 WAN ports.
The S/UNI APEX provides per-VC queuing for 64K VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS.

FEATURES
• Monolithic single chip ATM traffic manager providing VC queuing/shaping and VC, Class Of Service(COS), and Port scheduling, congestion management, and switching across 2048 ports.
• Targeted at systems where many low speed ATM data ports are multiplexed onto few high speed ports.
• 869 Kcells/s non shaped throughput in full duplex.
• 1.73 Mcells/s non shaped throughput in half duplex.
• 1.42 Mcells/s shaped throughput (aggregate of the four shapers)
• Supports four WAN uplink ports, with port aliasing
• Supports 2048 loop ports. Loop port can support an uncongested rate up to 230Kcells/sec.
• Provides 4 Classes of Service per port with configurable traffic parameters enabling support for a mix of CBR, VBR, GFR, and UBR classes.
• Provides 64k per-VC queues individually assignable to any COS in any port.
• Provides support of up to 256k cells of shared buffer
• Provides 2 independent cell emission schedulers, 1 for the WAN ports, and 1 for the Loop ports. The schedulers have the following features: Three level hierarchical cell emission scheduling at the port, class, and VC levels.
   • WAN Port Scheduling
      • Weighted Interleaved Round Robin WAN port scheduling.
      • Per port Priority Fair Queued class scheduling with port independence.
      • Per Class
         • Weighted Fair Queued VC scheduling with class independence or
         • Shaped Fair Queued VC scheduling applying rate based per VC shaping or
         • Frame Continuous Queued VC scheduling for VC Merge and packet re-assembly.
   • Loop Port Scheduling
      • Weighted Interleaved Round Robin Loop port scheduling.
      • Per port Priority Fair Queued class scheduling with port independence.
      • Per Class
         • Weighted Fair Queued VC scheduling with class independence or
         • Frame Continuous Queued scheduling for VC Merge and packet re-assembly
• Congestion Control applied per-VC, per-class, per-port and per-direction.
   • Flexible, progressive hierarchical throttling of buffer consumption. Provides sharing of resources during low congestion, memory reservation during high congestion.
   • Applies EPD and PPD on a per-VC, per-class, per-port, and per-direction basis with CLP differentiation, following emerging GFR standards.
   • Provides EFCI marking on a per VC basis.
   • Provides interrupts and indication of most recent VC/Class/Port that exceeded maximum thresholds.

APPLICATIONS
• DSL Access Multiplexers
• ATM Switches
• Multiservice Access Multiplexers
• 3rd generation wireless base stations and base station controllers
• OC-12 ingress congestion and traffic management
• OC-12 egress traffic manager and shaper