DESCRIPTION
The PM7346 S/UNI-QJET is a quad ATM physical layer processor with integrated DS3, E3, and J2 framers. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation.
The S/UNI-QJET contains integral DS3 framers, which provide DS3 framing and error accumulation in accordance with ANSI T1.107, and T1.107a, integral E3 framers, which provide E3 framing in accordance with ITU-T Recommendations G.832 and G.751, and integral J2 framers, which provide J2 framing in accordance with ITU-T Recommendation G.704 and I.432.
When configured for DS3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications.

FEATURES
• Single chip quad ATM User Network Interface operating at 44.736 Mbit/s,
   34.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-94-
   0406R5, and AF-PHY-0029.000. Each line can be individually configured for
   the desired rate.
• Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2
   transmission systems according to ITU-T Recommendation G.804.
• Provides a UTOPIA Level 2 compatible ATM-PHY Interface.
• Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and
   DS3 transmission systems according to the ATM Forum User Network
   Interface Specification and ANSI TA-TSY-000773, TA-TSY-000772, and E1
   and E3 transmission systems according to the ETSI 300-269 and ETSI 300-
   270.
• Support is provided for SMDS and ATM mappings into various rate
   transmission systems as follows:
• Implements the ATM physical layer for Broadband ISDN according to ITU-T
   Recommendation I.432.
• Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers.
• Can be configured to be used solely as a DS3, E3, or J2 Framer.
• When configured to operate as a DS3, E3, or J2 Framer, gapped transmit and
   receive clocks can be optionally generated for interface to devices which only
   need access to payload data bits.
• Provides support for an arbitrary rate external transmission system interface
   up to a maximum rate of 52 Mbit/s which enables the S/UNI-QJET to be used
   as a quad ATM cell delineator.
• Uses the PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, and
   PM6344 EQUAD T1 and E1 framer/line interface chips for DS1 and E1
   applications.
• Provides programmable pseudo-random test pattern generation, detection,
   and analysis features.
• Provides integral transmit and receive HDLC controllers with 128-byte FIFO
   depths.
• Provides performance monitoring counters suitable for accumulation periods
   of up to 1 second.
• Provides an 8-bit microprocessor interface for configuration, control and
   status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
   test purposes.
• Low power 3.3V CMOS technology with 5V tolerant inputs.
• Available in a high density 256-pin SBGA package (27mm x 27mm).

APPLICATIONS
• ATM or SMDS Switches, Multiplexers, and Routers
• SONET/SDH Mux E3/DS3 Tributary Interfaces
• PDH Mux J2/E3/DS3 Line Interfaces
• DS3/E3/J2 Digital Cross Connect Interfaces
• DS3/E3/J2 PPP Internet Access Interfaces
• DS3/E3/J2 Frame Relay Interfaces