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PM7375 数据表 (PDF) - PMC-Sierra, Inc

PM7375 Datasheet PDF - PMC-Sierra, Inc
部件名 PM7375
下载  PM7375 下载
文件大小   119.59 Kbytes
  4 Pages
制造商  PMC [PMC-Sierra, Inc]
网页  http://www.pmc-sierra.com
标志 PMC - PMC-Sierra, Inc
功能描述 ATM SAR and PHY Processor for PCI Bus

PM7375 Datasheet (PDF)

Go To PDF Page 下载 数据表
PM7375 Datasheet PDF - PMC-Sierra, Inc

部件名 PM7375
下载  PM7375 Click to download

文件大小   119.59 Kbytes
  4 Pages
制造商  PMC [PMC-Sierra, Inc]
网页  http://www.pmc-sierra.com
标志 PMC - PMC-Sierra, Inc
功能描述 ATM SAR and PHY Processor for PCI Bus

PM7375 数据表 (HTML) - PMC-Sierra, Inc


PM7375 产品详情

DESCRIPTION
The PM7375 LASAR-155 Local ATM Segmentation and Reassembly & Physical Layer device is a monolithic integrated circuit that implements SONET/SDH transmission convergence, ATM cell mapping, ATM Adaptation Layer, and PCI Bus memory management functions for a 155.52 or 51.84 Mbit/s ATM User Network Interface.

FEATURES
• Single-chip Peripheral Component Interface (PCI) Bus Local ATM Network Interface using SONET/SDH framing at 155.52 or 51.84 Mbit/s and ATM Adaptation Layer 5 (AAL-5).
• Implements the ATM Physical Layer according to the ATM Forum User Network Interface Specification and ITU-TS Recommendation I.432, and the ATM Adaptation Layer Type 5 (AAL-5) for Broadband ISDN according to ITU-TS Recommendation I.363.
• Provides a direct interface to multimode or single mode optical modules or twisted pair wiring (UTP-5) modules, with on-chip clock recovery and clock synthesis.
• Directly supports a 32-bit PCI bus interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities. Other 32 bit system buses can be accommodated using external glue logic.
• Provides an on-chip 96 cell receive buffer to accommodate up to 270 µs of PCI Bus latency.
• Provides a optional microprocessor port with master and slave capabilities.
• Provides a SCI-PHY and Utopia compliant interface for connection to external PHY layer devices.
• Supports simultaneous segmentation and reassembly of 128 virtual circuits (VCs) in both transmit and receive directions.
• Provides leaky bucket peak cell rate enforcement using 8 programmable peak queues coupled with sub peak control on a per VC basis; provides sustainable cell rate enforcement using the programmable peak cell rate queues and per VC token bucket averaging; and provides aggregate peak cell rate enforcement.
• Provides a generic constant bit-rate (CBR) port.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Low power, 0.6 micron, +5 Volt CMOS technology.
• 208 copper slugged plastic quad flat pack (PQFP) package.

APPLICATIONS
• ATM Workstations and Servers
• ATM Bridges, Switches and Hubs
• Multimedia Terminals




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