DESCRIPTION
The PM7380 FREEDM-32P672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 672 bi-directional channels.
The FREEDM-32P672 may be configured to support H-MVIP, channelised T1/J1/E1 or unchannelised traffic across 32 physical links.

FEATURES
• Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/ gather capabilities.
• Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are grouped into 4 logical groups of 8 links. A common clock and a type 0 frame pulse is shared among links in each logical group. The number of time-slots assigned to an HDLC channel is programmable from 1 to 32.
• Supports up to 672 bi-directional HDLC channels assigned to a maximum of 8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a common clock and a type 0 frame pulse. The number of time-slots assigned to an HDLC channel is programmable from 1 to 128.
• Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelised T1/J1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).
• Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link, subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a clock rate of up to 10 MHz.
• Supports three bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz.
• Supports a mix of up to 32 channelised, unchannelised and H-MVIP links, subject to the constraint of a maximum of 672 channels and a maximum aggregate link clock rate of 64 MHz in each direction.
• Links configured for channelised T1/J1/E1 or unchannelised operation support the gapped-clock method for determining time-slots which is backwards compatible with the FREEDM-8 and FREEDM-32 devices.
• For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
• For each channel, the receiver checks for packet abort sequences, octet •ligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value.
• Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.
• For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
• For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.
• Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.
• Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.
• Provides 32 Kbytes of on-chip memory for partial packet buffering in both the •ransmit and receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering.
• Supports PCI burst sizes of up to 256 bytes for transfers of packet data.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board •est purposes.
• Supports 3.3 Volt PCI signaling environments.
• Supports 5 Volt tolerant I/O (except PCI).
• Low power 2.5 Volt 0.25 μm CMOS technology.
• 329 pin plastic ball grid array (PBGA) package.

APPLICATIONS
• IETF PPP interfaces for routers
• TDM switches
• Frame Relay interfaces for ATM or Frame Relay switches and multiplexors
• FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors.
• Internet/Intranet access equipment.
• Packet-based DSLAM equipment.