Features
• High Voltage Types (20V Rating)
• Bidirectional Parallel Data Input
• Parallel or Serial Inputs/Parallel Outputs
• Asynchronous or Synchronous Parallel Data Loading
• Parallel Data-Input Enable on “A” Data Lines (3-State
Output)
• Data Recirculation for Register Expansion
• Multipackage Register Expansion
• Fully Static Operation DC-to-10MHz (typ.) at
VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1μA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Parallel Input/Parallel Output, Serial Input/Parallel Output,
Serial Input/Serial Output Register
• Shift Right/Shift Left Register
• Shift Right/Shift Left With Parallel Loading
• Address Register
• Buffer Register
• Bus System Register with Enable Parallel Lines at Bus
Side
• Double Bus Register System
• Up-Down Johnson or Ring Counter
• Pseudo-Random Code Generators
• Sample and Hold Register (Storage, Counting,
Display)
• Frequency and Phase Comparator

Description
CD4034BMS is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate) parallel
data, or 4) accept parallel data from either of two buses
and convert that data to serial form. Inputs that control the
operations include a single-phase CLOCK (CL), A DATA
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S),
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/
SERIAL (P/S).
Data inputs include 16 bidirectional parallel data lines of
which the eight A data lines are inputs (3-state outputs) and
the B data lines are outputs (inputs) depending on the signal
level on the A/B input. In addition, an input for SERIAL DATA
is also provided.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave. Isolation from external noise and the effects
of loading is provided by output buffering.