2-V to 6-V Operation
Fully Static Operation
Buffered Inputs
Common Reset
Positive-Edge Clocking
Balanced Propagation Delay and Transition
Times
High Noise Immunity: NIL = 30%, NIH = 30%
of VCC at VCC = 5 V
Packaged in Ceramic (F) DIP Package and
Also Available in Chip Form (H)

description
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each
decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.
Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE)
input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C.