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CY74FCT157ATSOC.B 数据表 (PDF) - Texas Instruments

CY74FCT157ATSOC.B Datasheet PDF - Texas Instruments
部件名 CY74FCT157ATSOC.B
下载  CY74FCT157ATSOC.B 下载
文件大小   237.92 Kbytes
页   12 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 QUAD 2-INPUT MULTIPLEXERS WITH 3-STATE OUTPUTS

CY74FCT157ATSOC.B Datasheet (PDF)

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CY74FCT157ATSOC.B Datasheet PDF - Texas Instruments

部件名 CY74FCT157ATSOC.B
下载  CY74FCT157ATSOC.B Click to download

文件大小   237.92 Kbytes
页   12 Pages
制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments
功能描述 QUAD 2-INPUT MULTIPLEXERS WITH 3-STATE OUTPUTS

CY74FCT157ATSOC.B 数据表 (HTML) - Texas Instruments


CY74FCT157ATSOC.B 产品详情

Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CY54FCT157T
– 32-mA Output Sink Current
– 12-mA Output Source Current
CY74FCT157T
– 64-mA Output Sink Current
– 32-mA Output Source Current
3-State Outputs

description
The ’FCT157T devices are quad two-input multiplexers that select four bits of data from two sources under the
control of a common data-select (S) input. The output-enable (E) input is active low. When E is high, all of the
outputs (Y) are forced low, regardless of all other input conditions.
Moving data from two groups of registers to four common output buses is a common use of the ’FCT157T
devices. The state of S determines the particular register from which the data comes. It also can be used as
a function generator. These devices are useful for implementing highly irregular logic by generating any 4 of
the 16 different functions of 2 variables, with 1 variable common.
The ’FCT157T devices are logic implementations of a four-pole, two-position switch, where the position of the
switch is determined by the logic levels at S.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.




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