Features
• Common Clock and Asynchronous Reset on Four
D-Type Flip-Flops
• Positive Edge Pulse Triggering
• Complementary Outputs
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description
The ’HC175 and ’HCT175 are high speed Quad D-type Flip-
Flops with individual D-inputs and Q, Q complementary
outputs. The devices are fabricated using silicon gate CMOS
technology. They have the low power consumption
advantage of standard CMOS ICs and the ability to drive 10
LSTTL devices.
Information at the D input is transferred to the Q, Q outputs on
the positive going edge of the clock pulse. All four Flip-Flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All four Q outputs are reset to a
logic 0 and all four Q outputs to a logic 1.