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CD4541BCM 数据表 (PDF) - SYC Electronica

CD4541BCM Datasheet PDF - SYC Electronica
部件名 CD4541BCM
下载  CD4541BCM 下载
文件大小   117.04 Kbytes
  8 Pages
制造商  SYC [SYC Electronica]
网页  https://www.sycelectronica.com.ar/index.php
标志 SYC - SYC Electronica
功能描述 Programmable Timer

CD4541BCM Datasheet (PDF)

Go To PDF Page 下载 数据表
CD4541BCM Datasheet PDF - SYC Electronica

部件名 CD4541BCM
下载  CD4541BCM Click to download

文件大小   117.04 Kbytes
  8 Pages
制造商  SYC [SYC Electronica]
网页  https://www.sycelectronica.com.ar/index.php
标志 SYC - SYC Electronica
功能描述 Programmable Timer

CD4541BCM 数据表 (HTML) - SYC Electronica


CD4541BCM 产品详情

General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special features
of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC network.
The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.

Features
 Available division ratios 28, 210, 213, or 216
 Increments on positive edge clock transitions
 Built-in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over processing
@ < 10 kHz)
 Oscillator frequency range ≈ DC to 100 kHz
 Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
 Automatic reset initializes all counters when power turns
on
 External master reset totally independent of automatic
reset operation
 Operates at 2n frequency divider or single transition
timer
 Q/Q select provides output logic level flexibility
 Reset (auto or master) disables oscillator during resetting
to provide no active power dissipation
 Clock conditioning circuit permits operation with very
slow clock rise and fall times
 Wide supply voltage range—3.0V to 15V
 High noise immunity—0.45 VDD (typ.)
 5V–10V–15V parameter ratings
 Symmetrical output characteristics
 Maximum input leakage 1 μA at 15V over full temperature
range
 High output drive (pin 8) min. one TTL load




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